Tool/software:
The following questions are based on the following assumptions:
- Peripheral Mode
- Transmit-and-Receive Mode
- Using SPI0
- Both TX and RX built-in FIFO are used
- DMA is not used
[Question 1]
When using McSPI in Slave mode, I understand that the SINGLE bit in the MODULCTRL register should be set to 1. Additionally, according to the TRM (Table 13-22), multi-channel operation appears to be applicable only in master mode (i.e., Controller Mode). However, in my environment, I was unable to generate an EOW interrupt with this setting. When I changed the SINGLE bit in the MODULCTRL register to 0 in the same environment, I was able to observe the EOW interrupt occurring.
I would like to understand this phenomenon. How does the SINGLE bit in the MODULCTRL register affect peripheral mode operation?
[Question 2]
Is it possible to trigger an interrupt upon the completion of SPI communication (i.e., on the inactive edge of CS)?
Additionally, can the "End of Word Count" interrupt be used for this purpose?
In scenarios where the data size sent from the controller is unknown beforehand, I want to detect the end of SPI communication by using the inactive edge of CS as a trigger.
The TRM (Section 13.3.3.2.5) states that the End of Word Count interrupt includes the “SPI transfer has halted” condition.
I believe I can use the EOW interrupt for this purpose and have tried the following configuration ( and sending 8 bytes from the master) :
IRQENABLE = 0x00020000; // Enable EOW
XFERLEVEL = 0xFFFF0F00; // WCNT = max, AFL=15
However, the EOW bit in the IRQSTATUS register was not set upon the inactive edge of CS.
I would like to clarify whether this is due to a misconfiguration or if it is fundamentally impossible to achieve this behavior.
