IWRL6432AOP: Interrupt muxing for PWM interrupt

Tool/software:

Hello,

I'm trying to understand the ePWM example, and how interrupt muxing works on the IWRL6432AOP.

There's a step in the example where the code reads some raw register values for the CSL_APP_CTRL_U_BASE and then writes back a raw hex value of 0x80:

 /* Configure Mux for PWM interrupt generation */
    regVal = HW_RD_REG32(CSL_APP_CTRL_U_BASE + CSL_APP_CTRL_APPSS_IRQ_REQ_SEL);
    regVal = (regVal & ~(0xC0)) | 0x80;
    HW_WR_REG32(CSL_APP_CTRL_U_BASE + CSL_APP_CTRL_APPSS_IRQ_REQ_SEL, regVal);

It seems like high level this should correspond with the interrupt number in this table in the TRM for APPSS interrupt mapping:

But 0x80 isn't 48 and the TRM doesn't actually indicate which bit value the EPWM channel interrupts correspond to in APP_CTRL:APPSS_IRQ_REQ_SEL. Some of the other entries in this table have an array index indicator which I assume corresponds to which bit to set in this register.

Can someone explain how this works? Also, we should not be using raw hex values in our examples unless it is documented somewhere what the value is.

Thanks,

Munan