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TMP127-Q1: Can FPGA interface with TMP127-Q1 by only SIO and SCLK but leave Chip Select low all the time?

Lawrence Chen
Prodigy 20 points
Part Number: TMP127-Q1
Other Parts Discussed in Thread: TMP127, TMP1826

Tool/software:

Hi,

Current FPGA only has two 3.3V unused IO.  Can it interface with TMP127-Q1 via SIO and SCLK then leave CS stays low all the time?

Thanks,

Lawrence

  • 0
    TI__Mastermind 43815 points

    The TMP127 alternates between 16 bit reads and 16 bit writes while CS is held. If your controller can change direction of SIO pin, it may be possible to implement. However, there is a danger of losing clock sync. From the moment of power-on, if there is ever an unexpected SCLK event, there is no way to clear it and synchronize with the TMP127 without CS. I don't recommend.

    We have a large portfolio of I2C devices that operate over two-pin interface. We also have TMP1826 with 1-Wire interface.

    thanks,

    ren