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IWRL6432AOP: Questions on PROTSET/PROTCLR, PWRDWNSET, and MSTID Bits in PCR Registers (xWRLx432 TRM)

Sato Hiroyasu
Prodigy 120 points
Part Number: IWRL6432AOP

Tool/software:

Hello,
I have a few questions regarding the PCR registers in the xWRLx432 Technical Reference Manual. I would appreciate any clarification.

Q1:
Are the PROTSET and PROTCLR bits used to control access permissions (read/write in user or privileged mode) for the corresponding peripherals?

Q2:
When setting a bit to 1 in the PWRDWNSET bitfield, does it mean the clock to the corresponding peripheral should be powered down?
In what kind of use cases is setting 1 in this bit typically expected?

Q3:
I’m not sure how to use the MSTID bit, possibly because I don’t fully understand what a “controller-ID” is.
Could you please explain what “controller-ID” refers to?

Thank you very much for your support.

  • 0
    TI__Mastermind 40555 points

    HI, there:

    We will get back to you in a day or two.

    Best,

    Zigang

  • 0 in reply to zigang Yang
    Prodigy 120 points

    Hello Zigang,
    Thank you for your continued support.

    We appreciate the proposed schedule, and we look forward to your response.
    Please let us know if there are any updates or changes.

    Best regards,
    Hiroyasu Sato

  • 0 in reply to Sato Hiroyasu
    TI__Intellectual 2340 points

    Hi Sato,

    Find the answers for the respective questions below:

    1. Yes, these control access permission (user, privileged mode) for every corresponding PS, PCS regions.
    2. This PWRDWNSET bit field can be leveraged for clock-gating purposes. We have not verified or deployed it in any of the radar devices.
    3. This is additional access control based on MSTID (16 MSTIDs are supported in PCR). So, in SoC using ISC register space the PRIVID of the master can be pre decided. So once PRIVID is decided for a master then every-region in PCR can be configured to decide what all PRIVIDs can access it.

    Regards,

    Sreedeep

  • 0 in reply to Sreedeep K S
    Prodigy 120 points

    Hello,

    Thanks for your reply.

    Q1 and Q2 are resolved.
    I’d like to ask a couple of follow-up questions regarding Q3. I’m still not fully clear on the ISC register space:

    • Q3-a: Is MSTID an ID for bus masters (e.g., CPU cores), and does the MSTID bit in the PCR register control access permissions for each PCR region per bus master?

    • Q3-b: Regarding the ISC register space — does it provide functionality to control MSTID permissions?

    Appreciate your support.

  • 0 in reply to Sato Hiroyasu
    TI__Intellectual 2340 points

    Hi,

    a: MSTID is the term defined for infrastructure components which are the static values mostly pre-decided. PCR is inherently developed for MSTID based blocking that is why everywhere in the document it is mentioned as “Master-ID blocking”.

    But in all radar devices so far, there are more than 16 master, so we leveraged another sideband signal in the VBUSM, VBUSP protocols called “privid” , by connecting it from an MMR-registers to make it configurable for each master. And at PCR also instead MSTID the “PRIVID” from the interconnect is used. By doing this we can group multiple physical MSTIDs into a single privid and the corresponding privid blocking/unblocking is decided at the PCR.

    b: As mentioned above, ISC register space decides what is the PRIVID value for any master.

    Regards,

    Sreedeep

  • +1 in reply to Sreedeep K S
    Prodigy 120 points

    Hi Sreedeep,

    Thank you very much for your detailed explanation.
    The questions are now fully resolved. Your support and clear guidance are much appreciated.

    Best regards