Tool/software:
Hello,
My use case is running a range-bin by range-bin VFFT pipeline inside the HWA:
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PS0: BFP decompression (input from L3 -> HWA RAM)
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PS1: FFT
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PS2: BFP compression of FFT output
Currently I am handling input this way:
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CPU triggers an EDMA transfer(using EDMACCPaRAMEntry) for one rbin from L3 to HWA RAM.
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CPU then triggers PS0 by software.
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Wait for completion, repeat in a for-loop for every rbin. (for loop for updating srcAddr to point at the next rBin)
This works but is inefficient because the CPU is tied up driving EDMA for each rbin.
Goal:
Eliminate the CPU for-loop. I would like:
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The first EDMA transfer to be kicked manually by the CPU.
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When EDMA completes, it should trigger PS0 start
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When PS0 finishes, it should trigger a DMA request back to EDMA to start the next rbin transfer automatically.
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This sequence should repeat until all rbins are processed, with no CPU intervention.
Questions:
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Is this flow supported by HWA?
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EDMA completion -> trigger to start PS0.
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HWA PS0 done -> triggers edma -> EDMA event for next transfer.
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In the HWA paramset configuration:
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For PS0, should I set
triggerMode = HWA_TRIG_MODE_DMA
and enable dma request ininterrupt Cfg
? -
Which
dmaRequestLine
value should be used to connect PS0 completion back to EDMA?
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On the EDMA side:
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Should I build a linked PaRAM list (one per rbin), with the channel bound to the HWA DMAREQ line?
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How do I route the chosen EDMA TCC completion to
HWA_TRIG_IN0
so PS0 gets triggered correctly?
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- Also can you explain the concept of the field 'headerEnable' field in Compression?