Other Parts Discussed in Thread: AWR2944
Tool/software:
Hello.
Currently i'm trying to bring up the HIL playback demo on the AWR2944 ( Proc113 - Rev.D ) , We've our own Xilinx FPGA that we're using to transmit MIPI CSI2 frames in order to playback radar sensor data.
Based on your recommendation we understood that the HIL Demo provided by TI was done on a different version of the SoC , and we that we needed to adapt the application to our version.
Since then I have been using CCS 12.8.1 and mcuplus_sdk_04_04_01_02 , I used one of the driver examples provided in the package , and proceeded to add one CSIRX instance.
the target of this is to startup the CSIRX core , send some mipi lines from my system(FPGA) and be able to see an interrupt or a callback function being called or a print on the UART when the frames are sent.
however I was unable to get any reaction from the SW , and tried many different configurations to no avail.
I have a few points I thought you might be able to help me understand.
1- I checked the board schematics and found that the CSI lines were not connected
so i installed 0 ohm resistors in R135,R138,R168,R189,R191,R192 and removed the 0 ohm resistor R196.
can you please confirm that this change is correct ?
2- can you help me understand how the DPHY clock option maps to the mipi line rate.
so in my case the FPGA will send data at 600 Mbps per lane , then in that case what should the DPHY clock be at ?.
3- I saw in the HIL demo that was shared , a mention of a change that needs to be done in the bootloader.
is this related to the CSIRX core and is it needed to receive from the core ?
4 - can you refer to this thread here -> AWR2944: receive data from CSI2
it was recommended in the thread to modify Drivers_csirxInstanceOpen , so that it blocks until the transmitter starts shooting , is this necessary for the core to work ? ( without this modification i mostly get "CSIRX_complexioIsResetDone failed" when phyEnable is set to true )
5- provided the .syscfg for my simple application , it is based off the hello_world example and modified to add the csirx core , can you let me know if i'm missing anything here ?.
/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "AWR294X" --part "Default" --package "ETS" --context "r5fss0-0" --product "MCU_PLUS_SDK_AWR2944@09.02.00"
* @v2CliArgs --device "AWR2944" --package "FCCSP (ALT)" --context "r5fss0-0" --product "MCU_PLUS_SDK_AWR2944@09.02.00"
* @versions {"tool":"1.21.0+3721"}
*/
/**
* Import the modules used in this configuration.
*/
const csirx = scripting.addModule("/drivers/csirx/csirx", {}, false);
const csirx1 = csirx.addInstance();
const clock = scripting.addModule("/kernel/dpl/clock");
const debug_log = scripting.addModule("/kernel/dpl/debug_log");
const mpu_armv7 = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71 = mpu_armv7.addInstance();
const mpu_armv72 = mpu_armv7.addInstance();
const mpu_armv73 = mpu_armv7.addInstance();
const mpu_armv74 = mpu_armv7.addInstance();
const mpu_armv75 = mpu_armv7.addInstance();
const mpu_armv76 = mpu_armv7.addInstance();
/**
* Write custom configuration values to the imported modules.
*/
csirx1.$name = "CONFIG_CSIRX0";
csirx1.phyEnable = true;
csirx1.instOpenEnable = true;
csirx1.dphy.$name = "CONFIG_CSIRX_DPHY0";
csirx1.dphy.ddrClockInHz = 300000000;
csirx1.complexio.$name = "CONFIG_CSIRX_COMPLEXIO0";
csirx1.complexio.dataLane3_position = "CSIRX_LANE_POSITION_LANE_NOT_USED";
csirx1.complexio.dataLane2_position = "CSIRX_LANE_POSITION_LANE_NOT_USED";
csirx1.complexio.isAllLanesEnterULPM = true;
csirx1.complexio.isAllLanesExitULPM = true;
csirx1.complexio.isPowerAuto = true;
csirx1.common.$name = "CONFIG_CSIRX_COMMON0";
csirx1.common.isOcpError = true;
csirx1.common.isGenericShortPacketReceive = true;
csirx1.common.isOneBitShortPacketErrorCorrect = true;
csirx1.common.isMoreThanOneBitShortPacketErrorCannotCorrect = true;
csirx1.common.isComplexioError = true;
csirx1.common.isFifoOverflow = true;
csirx1.common.combinedEndOfLineCallback = "eol_cb";
csirx1.common.combinedEndOfLineCallbackArgs = "eol_cb_args";
csirx1.common.combinedEndOfFrameCallback = "eof_cb";
csirx1.common.combinedEndOfFrameCallbackArgs = "eof_cb_args";
csirx1.common.commonCallback = "common_cb";
csirx1.common.commonCallbackArgs = "common_cb_args";
csirx1.common.startOfFrameIntr0Callback = "sof0_cb";
csirx1.common.startOfFrameIntr0CallbackArgs = "sof0_cb_args";
csirx1.common.startOfFrameIntr1Callback = "sof1_cb";
csirx1.common.startOfFrameIntr1CallbackArgs = "sof1_cb_args";
csirx1.common.isHeaderErrorCheckEnabled = true;
csirx1.common.isSignExtensionEnabled = true;
csirx1.context[0].$name = "CONFIG_CSIRX_CONTEXT0";
csirx1.context[0].numLinesForIntr = 1;
csirx1.context[0].userDefinedMapping = "CSIRX_USER_DEFINED_FORMAT_RAW8";
csirx1.context[0].isEndOfLinePulseEnabled = true;
csirx1.context[0].isEndOfFramePulseEnabled = true;
csirx1.context[0].isPayloadChecksumEnable = true;
csirx1.context[0].isNumLines = true;
csirx1.context[0].isFramesToAcquire = true;
csirx1.context[0].isPayloadChecksumMismatch = true;
csirx1.context[0].isLineEndCodeDetect = true;
csirx1.context[0].isLineStartCodeDetect = true;
csirx1.context[0].isFrameStartCodeDetect = true;
csirx1.context[0].isFrameEndCodeDetect = true;
csirx1.context[0].isLongPacketOneBitErrorCorrect = true;
debug_log.enableUartLog = true;
debug_log.uartLog.$name = "CONFIG_UART0";
debug_log.uartLog.UART.$assign = "UARTA";
debug_log.uartLog.UART.RX.$assign = "PAD_DA";
debug_log.uartLog.UART.TX.$assign = "PAD_DB";
const edma = scripting.addModule("/drivers/edma/edma", {}, false);
const edma1 = edma.addInstance({}, false);
edma1.$name = "CONFIG_EDMA0";
debug_log.uartLog.edmaConfig = edma1;
edma1.edmaRmDmaCh[0].$name = "CONFIG_EDMA_RM0";
edma1.edmaRmQdmaCh[0].$name = "CONFIG_EDMA_RM1";
edma1.edmaRmTcc[0].$name = "CONFIG_EDMA_RM2";
edma1.edmaRmParam[0].$name = "CONFIG_EDMA_RM3";
edma1.edmaRmReservedDmaCh[0].$name = "CONFIG_EDMA_RM4";
mpu_armv71.$name = "CONFIG_MPU_REGION0";
mpu_armv71.attributes = "Device";
mpu_armv71.allowExecute = false;
mpu_armv72.$name = "CONFIG_MPU_REGION1";
mpu_armv72.size = 14;
mpu_armv73.$name = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr = 0x80000;
mpu_armv73.size = 14;
mpu_armv74.$name = "CONFIG_MPU_REGION3";
mpu_armv74.baseAddr = 0x10200000;
mpu_armv74.size = 20;
mpu_armv75.$name = "CONFIG_MPU_REGION4";
mpu_armv75.baseAddr = 0x102E0000;
mpu_armv75.size = 16;
mpu_armv75.attributes = "NonCached";
mpu_armv75.allowExecute = false;
mpu_armv76.$name = "CONFIG_MPU_REGION5";
mpu_armv76.baseAddr = 0xC5000000;
mpu_armv76.size = 13;
mpu_armv76.attributes = "NonCached";
mpu_armv76.allowExecute = false;
I hope this post is clear and thanks in advance.