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TMAG5170-Q1: Clock duty cycle requirements

Bryce Aberg
Prodigy 10 points
Part Number: TMAG5170-Q1
Other Parts Discussed in Thread: TMAG5170

Tool/software:

Hi, I'm looking at possibly using the TMAG5170-Q1 in an application with a SPI interface from the LTC6820 operating with a clock frequency up to 1 MHz. Long story short, the duty cycle of the clock signal input to the TMAG5170-Q1 cannot be guaranteed to be 50% or even in the range of 40-60%. 

So my question is: Beyond the interface timing requirements called out in the datasheet for this device, are there any duty cycle requirements?

Regards,

B

  • 0
    TI__Mastermind 21340 points

    Bryce,

    There shouldn't be any clock duty cycle requirements outside of the setup and hold requirements.  Both rising and falling edges matter, so you need to be sure that whichever portion of the clock cycle is shortest will satisfy the timing requirements from section 6.8.  That will include your ability to drive SDI and capture data from TMAG5170 on SDO.

    Thanks,

    Scott