IWRL6432AOP: TDM - delay between TXs ?

Geoffrey Ficara

Expert 4145 points

Part Number: IWRL6432AOP

Hi,

We would ike to understand :

how we can determine how much time there is between TX1 and TX2 ?
Once TX1/RX1,RX2,RX3 is received, do we wait until TX2/RX1,RX2,RX3 is achieved to transmit the paquet or do we send it as soon as TX1/RX1,RX2,RX3 is received?

Thank you,

Geoffrey

6 months ago

0 Pedrhom Nafisi 6 months ago

TI__Mastermind 29492 points

Hello Geoffrey,

1. For TDM, the time between the start of TX1 and start of TX2 is the chirping interval time which is ramp time + idle time.

2. I am guessing you are referring to receiving data from the DCA1000, which we send the packet on a chirp-by-chirp basis. We send TX1 data right as we get it and we need to buffer empty before TX2 comes in.

Best Regards,

Pedrhom

0 Geoffrey Ficara 6 months ago in reply to Pedrhom Nafisi

TI__Expert 4145 points

Hi Pedrhom,

1. Ok clear

2. Is it done by the FW or by the application ? In other words, can the customer decide to buffer TX1 and TX2 data before sending it to the host (DCA1000 or a MCU host) ?

Regards,

Geoffrey

+1 Pedrhom Nafisi 6 months ago in reply to Geoffrey Ficara

TI__Mastermind 29492 points

Hello Geoffrey ,

No because with the way it is setup, there is one buffer and thus TX2 would overwrite TX1.

Best Regards,

Pedrhom

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IWRL6432AOP: TDM - delay between TXs ?