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CLK selection of TDC7200EVM ?

Other Parts Discussed in Thread: MSP430F5529, TDC7200EVM, TDC7200

Hi, 

I am reading the source code of MSP430F5529 to control the TDC7200EVM, and I have some questions

1) Which CLK source is selected for the following example? 

Texas Instruments\TDC7200EVM\Firmware\TDC7200EVM_Firmware_Source-v1.10\code\demo_apps\demo1_tdc7200_basic_rw

I did not find the code to set high of  P1.6 of MSP430F5529, which connects to the STANDBY pin of Y1 (8MHZ OSC). I think setting high of STANDBY is needed. Or,does the example use CLK_EXT?

2) If I want to use Y1 (8MHZ OSC) to source the TDC7200EVM, should I enable the TDC7200 before or after enable the OSC?

3)

 

Does CALIB_CLK means the input CLK of TDC7200? So if I want to achieve the min standard deviation and max throughput of TDC7200, I need to input a 16 MHz to CLK pin and a 20MHz to SPI_CLK, right?

Thanks,

Eric

  • 1. The following two lines initializes the TDC7200 oscillator

    TI_TDC7200_OSCENABLE_PxOUT |= TI_TDC7200_OSCENABLE_PIN; // Set pin high: enable afe osc
    TI_TDC7200_OSCENABLE_PxDIR |= TI_TDC7200_OSCENABLE_PIN; // Set pin direction is output

    The TDC7200 oscillator enable pin as you point out is P1.6. In the first version of the board this was P8.1 and later moved to P1.6. The updated definition in the file TI_MSP430_hardware_board.h is P3.3 (incorrect). It should be P1.6. TDC7200 needs the clock input to function and looks like the default state of the pin P1.6 keeps the oscillator enabled.

    2. .You should enable the oscillator before enabling TDC7200. Give sufficient time to ensure the oscillator is running and stable before making measurements. I think you should give about 3000us for the oscillator to stabilize. Same way when TDC7200 is enabled it needs about 300us (typ) for POR to complete and power to stabilize.

    3. Yes, CALIB_CLK is the TDC7200 input clock.  Yes, use 16MHz input clock for minimum standard deviation. SPI clock is from the master and using 20MHz SPI gives maximum throughput.

    Thanks,

    Vishy