• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 614 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Capacitive to Digital Converter Evaluation Module FDC1004EVM

senthil kumar narayanan
Prodigy 40 points
Other Parts Discussed in Thread: FDC1004, FDC2214

HI

Kindly clarify the following queries.
1) Regarding the Shield pin.
2)How to use the Shield pin, what material should I use for shield pin , where to stick it?
3)There is statement called as "Maximum Offset Capacitance: 100 pF", what does it mean?
4) What does this statement mean by "Maximum Shield Load: 400 pF"?
5) How stable will the O/P be??
6)will it be effected by humiditity and other EM radatitions?


  • 0
    TI__Expert 7400 points

    Hi:

    For the shield, please refer to the application note on SHLDing located on the FDC1004 product folder.

    The maximum offset capacitance of 100pF refers to the capacitance offset that can be handled by the FDC1004 using the CAPDAC. Refer to the datasheet on how to use that.

    The SHLD drivers can only support up to a 400pF capacitive load. If the capacitive load is greater than that, the SHLDs will be ineffective.

    The output stability or resolution is determined by the sampling rate of 100S/s, 200S/s, or 400S/s. At 100S/s = 0.5fF rms noise, 200S/s = 0.7fF rms noise, and 400S/s = 1fF rms noise.

    Humidity will affect capacitance, but it will be a slow drift over time so that can be compensated in software. EM interference will be a problem for the FDC1004 due to the architecture. Check out the FDC2214 as it is more immune to these factors.

    Thanks

    -David Wang

    Capacitive Sensing Applications