CDK - INPUT CLKP ADC VSP5324

We are developing an interface between the ADC and a FPGA. The FPGA IO bank voltage is 2V5. According to ADC datasheet, even though the ADC power supply is 1V8, the input clock (CLKP ADC VSP5324) can operate in 3V3 CMOS level (single mode). Is that correct? We have seen in the CDK that you are using 1V8 in single mode. Therefore, our concerning is if it is possible to use 2V5 digital logic for the clock.