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LM92 I2C read timing

cafain
Mastermind 6755 points
Other Parts Discussed in Thread: LM92

Hi,

LM92　I2C read timing。

Data-sheet (SNIS110D) page13 Figure9 timing is asked.

"Ack" (Low) is output more than master next to D0.

I think the place and the master reads take NACK (High) out of the specification of the I2C.

"NACK" is expected by this timing, but is my idea wrong?

Please tell me. Best regards

  • 0
    TI__Expert 7220 points
    Hi cafain,

    In a typical I2C transaction a NACK from the master is sent at the end of D0. However, Figure 9 displays a non-typical transaction where the SDA line is held low starting at D7. The master will try to get out of this mode by sending additional clock pulses and try to get data from the SDA line and initiate a stop condition. Because this transaction includes additional steps apart from a typical transaction an ACK from the master is acceptable.

    -Michael Wong