OPT9221 4-lane serial mode

Mike Smith7

Other Parts Discussed in Thread: OPT9221

Hello,

I'm having an issue with switching the OPT9221 to use 4-lane SSI output.

I'm able to load the OPT9221 v23 firmware and get/set the I2C configuration registers just fine. I have worked out a very basic initialization sequence just to activate streaming and see the OPT9221 outputting data. When I do this it seems like the OPT9221 responds to every register setting I apply except for changing op_mode to serial.

Here is my init sequence after loading the firmware:

set TG reg 80h to 0x000001 // disable streaming

set DE reg 33h to 0x010030 // set sysclk_in to 24MHz

set DE reg 39h to 0x000620 // set to 4-lane serial op_mode, rising clk edge, 24MHz output freq

set TG reg 80h to 0x000000 // enable streaming

While I have streaming active, I can write to DE register 39h and change the op_clk_freq and op_clk_edge and see with an oscilloscope that the changes are taking effect, but when I try to change the op_mode the OPT9221 just continues with 8bit parallel out (oscilloscope shows data being output on all 8 bits and the chip select stays high). I am also able to write to DE register 40h and see the chip select polarity change. Basically the OPT9221 appears to be ignoring the op_mode bits and responding to everything else.

What is preventing the OPT9221 from entering 4-lane SSI mode? Are there other registers that need to be set as a pre-requisite for 4-lane SSI mode?

Thanks,

Mike Smtih

Hardware and Software Engineer

mike.smith@viionsystems.com

over 9 years ago

0 Mike Smith7 over 9 years ago

Prodigy 60 points

Hello,

Any ideas out there about why I can't enable either 1 or 4 lane SSI mode? Changing DE register 39h settings all have an effect on the oscilloscope, I can see the frequency and clock polarity change with the register is written to. I can even change the chip select polarity in reg 40h and see that take effect.

Why can I not enter either 1 or 4 lane SSI mode?

Regards,

Mike

0 Bharath Patil over 9 years ago in reply to Mike Smith7

TI__Intellectual 2030 points

Mike,

First of all, sorry for the late reply. We will do our best to avoid this in the future. Could you please tell us a bit about your board? Is it a OPT8241-CDK or is it a custom board? Meanwhile we will try to reproduce this issue first thing in the morning on Monday (1st Feb) and get back to you as soon as possible.

Regards

Bharath

0 Mike Smith7 over 9 years ago in reply to Bharath Patil

Prodigy 60 points

Hello Bharath,

We are working with a custom board that we've created. The OPT9221 interfaces with an FPGA. I am able to load the OPT9221 with its firmware and talk to it over I2C successfully. I can query and set registers on both 0x58 and 0x5C I2C addresses.

I am observing what happens to the output pins with an oscilloscope. My issue is that when I change the settings on register 39h of I2C address 0x5C, I can observe the changes on the output pins corresponding to changes in OP_CLK_EDGE and OP_CLK_FREQ bits, but not OP_MODE or OP_SERIAL_WIDTH. With the scope, I see activity on all 8 data lines, HD, VD, FE, and no activity on CS, regardless of OP_MODE bits.

Also, I know the CS output pin is connected because I can change its polarity in register 40h and observe it going low.

From my earlier post, you can see my initialization sequence is very basic, just the minimum (I figured) to get the output block going so I can continue with FPGA development to receive 4-lane SSI data.

I look forward to seeing if you are able to reproduce this.

Thanks,

Mike

0 Bharath Patil over 9 years ago in reply to Mike Smith7

TI__Intellectual 2030 points

Mike,

Thanks for the details. Can you please drop in a mail at ti-3dtof@list.ti.com? We can take this conversation forward privately and also have a conference call if necessary. This issue might have something to do with the current firmware revision.

Regards

0 None_feiyu over 9 years ago in reply to Bharath Patil

Expert 1320 points

Hi Bharath,

I'd also have quentison about OP_Mode Register (DE 39h),pls see below

1、In OPT9221 Datasheet Page 28 Table 20 Description,OP_MODE default mode is Generic parallel mode;

2、In OPT9221 Datasheet Page 64 Table87 Description,OP_MODE default mode isDVP mode;

I want to know,Which is right？

Regards

None

0 Bharath Patil over 9 years ago in reply to None_feiyu

TI__Intellectual 2030 points

Mike,

Sorry for the issue. OP_MODE –7.3.4.3.5 is correct : 0: Generic parallel mode, 1 : DVP mode , 2 :SSI mode.
The issue will be fixed in the datasheet soon in a new revision.

Regards

0 None_feiyu over 9 years ago in reply to Bharath Patil

Expert 1320 points

Hi Bharath,

Thanks for you quickly reply.

In Generic parallel mode, Reference opt9221 Datasheet Page 25. I have some question about this mode,pls see the follow :

Q1、In OPT8241-CDK-EVM Hardware Design sch file,I found VD singal(Net TFC_FRM_VD_OUT) does not Connect to FX2,

Why VD singal not Connect to FX2 ?

Q2、If I Wan to see the OPT9221 Output Data,Only set TG 80h Register to '0', that is enough? or need other Registers Setting?

Q3、Ready and overflow singal does work like that：

1、When overflow Active,it's means that OPT9221 stop sends it's Data;

2、Does Overflow,High Active or Low Avtice? I don't any information about this.

3、if overflow doesn't active,but Ready is active,it also means that OPT9221 stop sends it's Data until Ready goes Active?

about Q3, Do I understand right?

Regards

None

0 None_feiyu over 9 years ago in reply to None_feiyu

Expert 1320 points

Hi Bharath,

In Generic parallel mode, Reference opt9221 Datasheet Page 25. I have some question about this mode,pls see the follow :

Q1、In OPT8241-CDK-EVM Hardware Design sch file,I found VD singal(Net TFC_FRM_VD_OUT) does not Connect to FX2,

Why VD singal not Connect to FX2 ?

Q2、If I Wan to see the OPT9221 Output Data,Only set TG 80h Register to '0', that is enough? or need other Registers Setting?

Q3、Ready and overflow singal does work like that：

1、When overflow Active,it's means that OPT9221 stop sends it's Data;

2、Does Overflow,High Active or Low Avtice? I don't any information about this.

3、if overflow doesn't active,but Ready is active,it also means that OPT9221 stop sends it's Data until Ready goes Active?

about Q3, Do I understand right?

Regards

None

0 Bharath Patil over 9 years ago in reply to None_feiyu

TI__Intellectual 2030 points

A1. In the OPT8241-CDK, FX2 uses FE signal for detecting frame end. Therefore VD connection is not necessary.

A2. Yes. Just setting tg_dis to '0' should be sufficient to see some data.

A3. Overflow is active high. But Overflow is not used for any functionality. It is just an indication. The status of overflow can be read back using I2C register (op_overflow). OPT9221 will continue to send data even if overflow signal is asserted but ready is not diasserted. The only way to control OPT9221 data output is to use the ready signal (when fb_ready_en is set to '1'). Refer to Table-16 with description for fb_ready_en and fb_ready_pol in the datasheet.

Regards

0 None_feiyu over 9 years ago in reply to Bharath Patil

Expert 1320 points

Hi Bharath,

Thanks for you reply.

for A2: it seem like just setting tg_dis to '0' ,so we can observe the opt9221 output data(Depth data),all right?

for A3: if fb_ready_en is set to '0',so wther ready set to '1' or set to '0',it will not influence the opt9221 output data,all right?

Regards

None

0 Bharath Patil over 9 years ago in reply to None_feiyu

TI__Intellectual 2030 points

Your interpretation is correct.

Regards

0 None_feiyu over 9 years ago in reply to Bharath Patil

Expert 1320 points

Hi Bharath,

Thanks for you reply.

Q1、So it only look like the overflow is just Debug singal,all right?

Q2、The FX2 use FIFO Mode transfer OPT9221 output Data to PC? Because opt9221 output Data only control by ready signal,this signal is connector to FX2's FIFO FLAG A Pin, So,in fx2 firmware,we should set the Flag A reports the 'Programmable-level'status or set the Flag A report the 'full'status?

Thanks&Regards

None

0 None_feiyu over 9 years ago in reply to None_feiyu

Expert 1320 points

Hi Bharath,

if you feel convenient,please help me solve the above problem.

Thanks&Regards

None

0 Bharath Patil over 9 years ago in reply to None_feiyu

TI__Intellectual 2030 points

Hi,

The SSI issue will be fixed with the new OPT9221 firmware that will be available in about 3 weeks.

Regards

0 None_feiyu over 9 years ago in reply to Bharath Patil

Expert 1320 points

Hi Bharath,

Thanks for you reply.

What my question is the follow,not about ssi issue：

Q1、So it only look like the overflow is just Debug singal,all right?

Q2、The FX2 use FIFO Mode transfer OPT9221 output Data to PC? Because opt9221 output Data only control by ready signal,this signal is connector to FX2's FIFO FLAG A Pin, So,in fx2 firmware,we should set the Flag A reports the 'Programmable-level'status or set the Flag A report the 'full'status?

Thanks&Regards

None

0 Anand Gadiyar over 9 years ago in reply to None_feiyu

TI__Genius 15005 points

Hi None,

For A2: Yes, setting tg_dis=0 will cause the OPT9221 to start outputting data.
For A3: Yes, if fb_ready_en = 0, then the READY feedback signal is ignored, and the OPT9221 will continuously send data.

If you want to make the OPT9221 send data in a DVP-like pattern, you may also want to program the blk_blank_size parameter to an appropriate value as required by your receiving chip. This parameter controls the DVP horizontal blank period.

Best Regards,
Anand

0 None_feiyu over 9 years ago in reply to Anand Gadiyar

Expert 1320 points

Hi Anand,

Thanks for you reply.

now i am how to work about ready and overflow.

Another question:

Q1: I think the FX2 should always work in slave FIFO mode,in my understand,the Ready signal of OPT9221 should connect to FIFO FLAG A reports the 'Programmable-level'status,now I do this,the opt9221 only sent a little data,then,stop send Data to FX2,but I set the Flag A report the 'full'status,it works well?

I am confused,why set Flag A reports the 'Programmable-level'status,it will not work well?

Thanks&Regards

None

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OPT9221 4-lane serial mode