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TMP103 I2C timing for Standard Mode

Jerry Chu
Genius 4915 points
Other Parts Discussed in Thread: TMP103

Hi Expert,

My customer used the I2C standard mode(100KHz) to test TMP103.  They want to verify the timing, but TMP103 and many TI datasheet didn't show the standard mode timing data. Do you have other TI document to mention it? Would you share it to me? Thanks!

  • 0
    TI__Mastermind 41235 points
    Our standard mode timing requirements are the same as our fast mode timing requirements. You'll note that our fSCL goes down to 1kHz in both modes that we specify.

    The difference between fast mode and high-speed mode is the high-speed command, which tells our device to change its input filters. This is what causes the change in timing requirements, and this is also why there is no change for standard mode.

    Ren
  • 0 in reply to Ren Schackmann
    Genius 4915 points

    Hi Ren,

    But it's quite difference between I2C Spec. Do you know why? Thanks!

  • 0 in reply to Jerry Chu
    TI__Mastermind 41235 points

    In the case of the I2C master controlling the SDA line, TMP103 needs the master to maintain the current SDA state for at least 20ns (in standard or fast modes) after the SCL has fallen. Despite the claim of zero, the I2C specification also requires that the data is maintained until after the SCL has fallen. See the attached image. We have elected to specify an actual characterized value instead of an ambiguous zero.

    If a master that changes data within 20ns of the fall of SCL is used with TMP103, TMP103 will misinterpret the address being sent, and will take no action. This means it will not acknowledge, read or write.

    Note that 20ns is 1/500th of a clock cycle at the frequency you're asking about, and is unlikely to be noticeable.

    Ren