offset - page 14 of datasheet of TDC7200

duuk lee

Other Parts Discussed in Thread: TDC7200

Hello,

From TDC7200 datasheet, I wonder the following two questions:

1). what does it mean for 'offset' mentioned on page14, section 8.4.1, line 5th - since there is no other more related information provided.

That sentence is :

"There is also an offset error in the measurement due to certain internal delays in the device."

2). on page28, Table 5, bit'0' is "NEW_MEAS_MASK" - what is this bit for ?

3). on page 28, Table 5, if overflow bits are disabled, then what happen if no 'STOP' pulse provided to TDC7200 ?

THanks !

over 9 years ago

0 duuk lee over 9 years ago

Intellectual 290 points

Sorry for my typo - actually there are three questions on different topics, not just offset . Thanks !

0 Vishy Viswanathan over 9 years ago in reply to duuk lee

TI__Mastermind 21685 points

1) It's a constant measurement offset that gets cancelled in calibration.

2) You can use "NEW_MEAS_MASK" bit to enable or disable the new measurement completion interrupt. If this bit is 1, INTB will be asserted at the successful completion of a measurement. Otherwise, only the corresponding status NEW_MEAS_INT bit in INT_STATUS register is set but the pin will not be asserted.

3) If clock and coarse counter overflow interrupt bits are disabled and there is no 'STOP' pulse, the counters would overflow and the corresponding status bit (COARSE_CNTR_OVF_INT/CLOCK_CNTR_OVF_INT) is set but the pin will not be asserted.

Thanks,
Vishy

0 duuk lee over 9 years ago in reply to Vishy Viswanathan

Intellectual 290 points

Many thanks, Vishay - very helpful.

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offset - page 14 of datasheet of TDC7200