Can someone help me understand the sequence of events (with code/pseudo-code examples) to achieve this? I have successfully implemented SPI comms and can write/read configuration settings to the appropriate registers and I am now ready to read actual ADC values but I require a few more details on the functionality of the LMP90080 - specifically how the ADC_DOUT registers gets populated. I've got the channels configured as below:
#define TI_LMP90100_CH_SCAN_REG_VALUE (0xD8) /* ScanMode3, LAST_CH=CH3, FIRST_CH=CH0 */ //was 0xF0
#define TI_LMP90100_CH0_INPUTCN_REG_VALUE (0x81) /* enable sensor diagnostics, default ref, vinp 0 vinn 1 */
#define TI_LMP90100_CH0_CONFIG_REG_VALUE (0x77) /* CH0 Configuration: 214.65 SPS, Gain=8 (FGA off), buffer in signal path*/
#define TI_LMP90100_CH1_INPUTCN_REG_VALUE (0x93) /* enable sensor diagnostics, default ref, vinp 2 vinn 3 */
#define TI_LMP90100_CH1_CONFIG_REG_VALUE (0x77) /* CH1 config: 214.65 SPS, Gain=8 (FGA off), buffer in signal path */
#define TI_LMP90100_CH2_INPUTCN_REG_VALUE (0xA5) /* enable sensor diagnostics, default ref, vinp 4 vinn 5 */
#define TI_LMP90100_CH2_CONFIG_REG_VALUE (0x77) /* 214.65 SPS, Gain=8 (FGA off), buffer in signal path */
#define TI_LMP90100_CH3_INPUTCN_REG_VALUE (0xB7) /* enable sensor diagnostics, default ref, vinp 6 vinn 7 */
#define TI_LMP90100_CH3_CONFIG_REG_VALUE (0x77) /* 214.65 SPS, Gain=8 (FGA off), buffer in signal path */
And my circuit is wired up as follows:
|
Channel |
Positive Input |
Negative Input |
Variable |
|
0 |
VIN0 |
VIN1 |
RTD1_Exc |
|
1 |
VIN2 |
VIN3 |
RTD1_Sig |
|
2 |
VIN4 |
VIN5 |
RTD2_Sig |
|
3 |
VIN6 |
VIN7 |
RTD2_Exc |
Question is this: how do I know/control what channel is being read from ADC_DOUT in a given transaction given that I'm not using the streaming read/write protocol and I've disabled DRDYB? I've reviewed the manual and the afe firmware considerations documents in detail and the only clue I can find is that I may need to monitor the SAMPLED_CH bits in the SENDIAG_FLAGS register to determine what channel I will be getting when I read from ADC_DOUT. Please let me know if this interpretation is correct and, if so, what the behavior will be after ADC_DOUT has been read (for example, will SAMPLED_CH automatically increment through CH0->CH1->CH2->CH3->CH0->CH1, etc)? If this is incorrect, what is the proper way to handle this? Is there a mechanism for the firmware to configure which channel's data goes into ADC_DOUT?
Thanks in advance,
Tony
