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OPT3001 in synchronous mode: could not get it to convert!

Other Parts Discussed in Thread: OPT3001

Dear Experts,

One of my customers has the below issue when using OPT3001 for synchronous reads:

"I was using OPT3001 in Continuous mode (OPT continuously samples and converts) and I was reading the Result Register asynchronously.

The design required me to change this and make synchronous reads, which means I have to set the OPT3001 to single conversion mode, wait for the End-of-conversion signal in the INT line, afterwards I'll read the Result Register.

I've consulted the http://www.ti.com/lit/ds/symlink/opt3001.pdf and I've implemented the according to the specifications:

    1. I init my MSP430 hardware (I2C, ...);
    1. Write OPT3001 register LOWLIMIT_REG (0x02) with value 0xC000;
    1. Enable high2Low interrupts in pin of INT line;
    1. Write OPT3001 register CONFIG_REG (0x01) with value 0xCA10 ( RN_AUTO | CT_800MS | M_SINGLE | L_SET )
    1. When interrupts occurs I disable further interrupts in INT and I'll flag it and I'll read RESULT_REG (0x00)
    1. When the result was received I'll write the CONFIG_REG (0x01) with value 0xCA10 ( RN_AUTO | CT_800MS | M_SINGLE | L_SET )
    1. go to 2

The problem is that it doesn't work! The only way to make it work is by reading the CONF_REG before writing it and in the datasheet is says: "The INT pin becomes inactive when the configuration register is read or the configuration register is written with a nonshutdown parameter or in response to an SMBus alert response." Well, I'm writing it, why doesn't it start the conversion I can't understand."

I would appreciate if someone gives an insight on this issue?

Thanks,

Murat Ilhan.

 

  • HI Murat,
    I tried to reproduce the problem in my lab, but everything is working as expected for me. Is it possible to check if I identified the command sequence to OPT3001 correctly ?
    Write: 02 C0 00
    Write: 01 CA 10
    Write: 00
    Read: <unique sample>
    Write: 01 CA 10
    Write: 00
    Read: <unique sample>

    I also tried the sequence:
    Write: 02 C0 00
    Write: 01 CA 10
    Write: 00
    Read: <unique sample>
    Write: 02 C0 00
    Write: 01 CA 10
    Write: 00
    Read: <unique sample>

    I did not constrain the timing by the interrupt action in this experiment, but I'm not clear that would be the issue.

    Thanks
    James