Hello Team,
Could you please look into the below for our customer.
-Omid
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I have been tasked with getting an FPGA interface to 4 DDC112 ADC’s connected serially working within the next 2 weeks.
I got some sample DDC112 FPGA code from TI. I have looked at sample code closely, and also studied the datasheets and App notes for this part.
There are a couple puzzling things that are simply not clear to me:
1) In the Sample FPGA Verilog code for the DDC112 - both the DDC_DATA_CAP.v and the DDC_ACQ_CONTROL.v modules generate independent DCLK outputs which are then OR’ed together inside the FPGA and the output of the OR gate is used to drive the DCLK input of the DDC112 chip.
I fully understand that the DDC_DATA_CAP.v needs to drive DCLK to shift out the data from the DDC112….. but why is the DDC_ACQ_CONTROL also driving the DCLK ?
Is the DDC_ACQ_CONTROL.v module driving the DCLK for the purpose of gating the DCLK signal coming from the DATA_CAP.v to delay the start of DCLK after DVALIDn has gone LO. There seem to be some comments in the code about a DCLK_WAIT state to do this. If that is the case…..then why doesn’t the DDC112 datasheet talk about the need to delay the start of DCLK after DVALIDn has gone LO. There is no mention of any such timing spec in the datasheet ??
2) It is not clear to me as to how I can get the State-machine on the DDC112 to get to Reset State (State 1 or 8) from the FPGA side without tracking the flow of the DDC112 State-machine on my FPGA. I really don’t want to do this because that mean mean timing each CONV pin transition. I need to get to the Reset State because our system needs to start a new capture everytime we get a trigger pulse.