LDC1000-Q1: Oscillator overloading simulation

ravindra r

Part Number: LDC1000-Q1

Hi,

We are trying to simulate oscillator overloaded (OSC DEAD bit in status register) condition in LDC1000-Q1 but we don't know how to simulate this.

We have connected 1MHz external crystal on Xin and Xout pins of LDC1000.

Please let me know how can i simulate the oscillator overloading condition upon which the OSC Dead bit gets set in the status register.

FYI, we have configured LDC as per our requirements and it seems to work perfectly fine. We just want to test the above mentioned negative test condition.

Hope to hear asap from you!

Thanks

Ravi

over 8 years ago

0 Ben Kasemsadeh over 8 years ago

TI__Genius 13650 points

Hello Ravi,
you should be able to simulate this scenario by opening the TBCLK/XIN pin connection. The OSC dead bit should be flagged and values in the inductance register field will be all zero.

0 ravindra r over 8 years ago in reply to Ben Kasemsadeh

Prodigy 20 points

Hi Ben,

Thanks for you reply.

As per your suggestion i tried disconnecting TBCLK/XIN pin connection with LDC1000. But the OSC_DEAD bit wasn't set in the status register.

Could you please let me know what could be the issue? Is there any other way from which we can simulate OSC_DEAD scenario?

Thanks,

Ravi

0 Ben Kasemsadeh over 8 years ago in reply to ravindra r

TI__Genius 13650 points

Hello Ravi,
I apologize; the bit refers to the sensor, not to the clock input. The bit may be a '1' if the sensor is short, if it is open, or if too few oscillation cycles occur in a given time period (also refer to the Watchdog timer frequency register).

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LDC1000-Q1: Oscillator overloading simulation