I'm using this part into a 2 transistor regenerative latch in a high noise RF environment (1/4" away from a 150W RF power transistor). I have generally eliminated noise issues, but I need to know what the power-up behavior of the TMP709 is because the latch following it may be active from 0.5V up to 5V. The TMP709 power supply is a zener regulated 5.1V, but depends on a customer-provided (28V) external power supply whose ramp-up profile is not known. I need to verify the TMP709's characteristic behavior (not specified, of course) between 0V and 2.7v to see under what conditions the latch may be triggered during a power-up event. The latch will trigger on about 10 ua of current sunk by the /OT pin, within 50 us. The supply will come up no faster than 2 ms (RC time constant of 2.43k/1uf bypass cap.)
The SET pin and /OT pin are each bypassed with 1 nF NP0 for RF suppression. Power supply bypass is 1 uf // 5.1V zener. Pullup R 44.2k to 5V.
ESD immunity at 28V side of power supply on PCB assy next to latch with en61000-4-2 ESD contact discharge parameters, except 200 ps rise time, latch trigger threshold (Criteria C) is +/- 10kv, contact discharge, about 1/2" away from the latch.