Hello,
I am trying to write FPGA code for AFE5809 to deserialize LVDS output.
Is there any written code/simulation that I can use for my FPGA?
Thank you.
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Hello,
I am trying to write FPGA code for AFE5809 to deserialize LVDS output.
Is there any written code/simulation that I can use for my FPGA?
Thank you.
Hi Praveen,
Thank you. More details:
I am using 10MHz ADC_Clock with 16 decimation factor. So, I can get sampling rate of 1.25MHz and I will get I-Q demodulated output on LVDS .
If you need anymore information please let me know! Thank you.
Regards,
Vatsal Naik