AWR1642: How to understand the L3 memory

Andy Yin

Part Number: AWR1642

Hi,

In the SWRU520, theDSS L3 memory is split into 8bank@128KB, with the first two banks reserved, and bank4~7 is shareable between MSS and DSS. Need your help to clarify my below questions, thank u very much.

1 In the AWR1642 ES1.0, there is only 640KB, how to map the 640KB with the bank0~7? What is the base address for each bank?

2 In the TRM it said Only Bank4~7 can be shareable and accessed by MSS R4F. But based on my test on EVM with below simple test code, all the L3 memory start from 0x51000000 to 0x5109FFFF can be accessed by MSS R4F. And I checked the register SHMEMBANKSEL3TO0=0x01010101, SHMEMBANKSEL3TO0=0x10010101.

int *gTestAddr;
int i;

gTestAddr = (int *)0x51000000;
for(i = 0; i < 0x28000; i++) //test 640KB
{
*gTestAddr = 0x12345678;
gTestAddr++;
}

BR,

Andy

over 8 years ago

0 Naveen Narayanan over 8 years ago

TI__Expert 5025 points

Hi Andy,

As you noted, there are 6 128 KB banks available to be allocated to the memories as listed in DSS_L3 memory organization section in the TRM SWRU520.

1. On AWR1642 ES1.0 samples, one bank (Bank 7) has to be allocated for the Radar Subsystem operation as captured in the AWR1642 Device Errata (DSS#06). So this leaves with 5*128KB = 640 KB that includes

Bank 2 and Bank 3 allocated by default to DSP L3
Bank 4, Bank 5 and Bank 6 available to be shared between DSP L3 and MSS CR4 TCMA/TCMB.

The allocated banks extend the addressable range of MSS CR4 TCMA and MSS CR4 TCMB. In case of DSP L3, the base address is 0x20000000 (as viewed from DSP subsystem) or 0x51000000 (as viewed from the Master Subsystem).

2. The memory allocated as DSS_L3RAM is accessible to both MSS as well as DSS as mentioned above. That's the reason you are able to write to them. The point regarding the sharing of memories is that only Banks 4 to Bank 7 are available to be allocated to MSS CR4 TCMA or MSS CR4 TCMB. Bank 2 and Bank3 are dedicated to DSS_L3RAM.

Additionally, as the allocation of memories need to be done before the ROM bootloader can load the respective program memories of the subsystems, the choice of shared memory allocation is exercised while creating a multicore image to be flashed onto the SerialDataFlash connected to the AWR1642 device. Please refer to the mmwave_sdk_user_guide.pdf and Image_Creator_User_Guide.pdf available in the mmWave SDK package. The memory allocation is done by the ROM bootloader based on the information provided in the MetaHeader.

Best regards,

Naveen

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AWR1642: How to understand the L3 memory