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AWR1243BOOST: Access to synthesizer signal on the pins

Part Number: AWR1243BOOST
Other Parts Discussed in Thread: AWR1243, UNIFLASH

Hi, 

Is there a possibility to access the divided down synthesizer signal on the AWR1243BOOST in CW mode and also during chirp mode? If it is possible, can you please guide me to the steps to make this happen. 

Thank you, 

RJ

  • Hello RJ,
    The divided down version of the synth can be brought out on the OSC_CLK_OUT pin. Synth/32 or Synth/16 can be brought out.
    If you are using the Radar studio the "Regop" tab has a debug signal option. There you can select the signal to be brought out on the OSC_CLK_OUT pin.

    Regards,
    Vivek
  • Thank you, Vivek. I do not see any OSC_CLK_OUT pin on the J5 and J6 connectors of AWR1243BOOST.
    Is there a place where the OSC_CLK_OUT pin location is shown ?
  • Hi Vivek,

    I also tried to get into Radar Studio and inside the RegOp tab, I tried to get the synth2.5G or synth5G, as a debug signal and the output message showed failed status.

    Thank you,

    RJ
  • Hello,
    On the AW1243/1443 EVM schematic sheet3, pinname OSC_CLKOUT, becomes signal AR_OSC_CLKOUT. On sheet 11, this goes to connector J2.

    The other pins that can be used, do not have traces on the EVM, FM_CW_CLKOUT, and FM_CW_SYNCOUT, these are the /4 cascade reference waveform pins.

    So I think you can monitor J2. Vivek will provide an update for software setup.

    Regards,
    Joe Quintal
  • Thanks Joe. I look forward to getting the information from Vivek.

    Now that there is a possibility of getting the synth output, is there a way also to get a some sort of a trigger signal on a chirp by chirp basis, like something of the nature of adc start on the AWR1243BOOST/DEVPACK ?

    Thanks!

    RJ
  • Hello There is a SYNC OUT pin to identify the start of a frame, not the start of a chirp.
    Regards,
    Joe Quintal
  • Hello RJ,
    As Joe pointed out , the OSC_CLKOUT signal can be observed on the J2 connector on the EVM.
    I am unable to see the error message you are seeing in the radar studio, could you post the image again? You can enable to clock outs once you have configured the front end.
    In the same "Regop" tab there is a "GPIO_O" configuration option where you can bring out the "ADC_valid" signal on the GPIO_0 pin. This signal indicates the ADC sampling period.

    regards,
    Vivek
  • Hi Vivek: Thank you for your reply. The output window of radar studio showing the error is attached below. There are two issues I have currently:

    1. OSC_CLK_OUT

    When I try to go to RegOp and configure the debug signal to be either 2.5G or 5G output, I get the Failed message which i believe is attached to ar1.WriteRegister function call.

    2. GPIO_O 

    When I configure this as ADC_VALID, I do not get any errors from the radar studio side which is great. However, I probed GPIO_0 on the mmwavedevpack and I am not able to see any activity on this pin. I am
    expecting a pulse at the beginning of adc data collection for every chirp.  

    I probed some other pins like the 3.3V and some other pins just to make sure that my set up is not an issue. 

    Thank you, 


    RJ

  • Hello RJ,
    In the snapshot you have sent I see that there is a warning of firmware mismatch. Have you downloaded the right BSS and MSS firmware that is available in the "\mmwave_dfp_00_07_00_04\rf_eval\rf_eval_firmware\radarss" and "\mmwave_dfp_00_07_00_04\rf_eval\rf_eval_firmware\masterss" paths of the DFP installation?
    Also you need to make sure that you pick the "xwr12xx_xwr14xx" one since you are using a AWR1243 EVM.

    Regards,
    Vivek
  • Hi Vivek,

    Thank you for your reply. I have downloaded the firmware BSS and MSS firmware from the file folder locations that you have mentioned in the post.

    Figure 1 below shows the radar studio window after SPI Connect but before RF Power Up. This shows the BSS and MSS firmware version. 

    Then when I click RF Power Up, the firmware versions are set to all zeros and the output window shows firmware version mismatch warning. Please see figure below. The current consumption goes up to 270 mA, and I have been able to get the AWR1243 to chirp and also be in CW mode. Of course the original problem mentioned in my previous post still stays. 

    Thank you for your help, Vivek ! 

    RJ

  • Additionally in the RegOp tab, any attempts to read the registers also results in an error.
  • Hello RJ,
    Looks like the SPI connect is not succeeding. Can you erase the onboard serial flash before you connect the radar studio? You can do that from Radar studio also by setting SOP mode 5 and clicking on "Flash program" without checking any of the check boxes beside the FW files locations. That should bring up a command prompt where it would try to connect to the COM port and erasing the flash.

    Alternatively you could also use the uniflash utility (www.ti.com/.../uniflash) based on the instructions in the SDK user guide (software-dl.ti.com/.../mmwave_sdk_user_guide.pdf).
    While using the Uniflash utility make sure you remove the radar EVM from the devpack board.

    Regards,
    Vivek
  • Thank you Vivek ! That was a good catch. After flashing the serial flash, I got rid of the firmware mismatch warnings. 

    I was able to get the 5GHz synth out and verify that it was following the trend of the chirp, and the sweeping the chirp bandwidth / 16. 

    However, I am still not able to get the ADC_VALID on the GIPIO_0. The software does not flash any errors, and everything passes when I select ADC_VALID in the RegOp tab.

    When I probe the GPIO_0 pin on the scope, I do not see any signal. May be there is a trick to it. Please note I am using AWR1243BOOST. 

    Thank you, 

    TJ

  • Hi Vivek,

    We found out that a 0 Ohm resistor needed to be connected on the AWR1243BOOST to get the signal out on GPIO_0. Once the resistor was installed, we were able to get the ADC_VALID signal out on the GPIO_0. The signal tracked the duration of the sampling time set up on the radar studio tool.

    Thank you and the team for your continual help and support, and a good catch on the SPI connect issue as well.

    Both issues related to this post have been resolved. 1) Synth out, 2) ADC_Valid Signal Out both accessible on the pins.

    Regards,

    RJ