AWR1243: general questions of using AWR1243 chipset

Hello Shai,
Here are some partial answers.
1) phase differences - in the cascade operation, 1 device is a Master as you have indicated. However ALL devices, even the master use the LO_IN for the FMCW reference. In this manner, using Figure 6-1 of the datasheet, (on the Master device, FM_CW_CLKOUT or FM_CW_SYNCOUT are driven ), this goes to a buffer amplifier, power divider. Each AWR1243 then receives a buffered and time delayed (equal trace delay routing) FM_CW_CLKIN or FM_CW_SYNCIN signal as the master chirp signal reference. The In to Out FM_CW signal delay, is not important, because the Master device is still using the FM_CW input signal.

related answer - AWR1243P - there is a device that enables the Tx phase shifter controls on each Tx output of each device. When the customer lays out the board, there are matching requirements for each of the (3) Tx outputs. If the customer has a specific Tx delay to antenna matching requirement for each element, the special characteristic of the AWR1243P may be needed. In section 5-7 of the datasheet, there is no Tx delay matching by Tx output specification. To adjust these phase delays on the special device, you would need to compare two Tx outputs either with gating a spectrum analyzer or time-sampling on an oscilloscope. You would then adjust the delays to your requirement.

2) there is no specification in section 5.7 of the datasheet for this. Looking at the AWR1243 EVM schematic, the FM_CW_CLKIN and FM_CW_SYNCIN signal inputs are GNDed, so this measurement can't be done on the EVM. As described in (1) , The Transmitter to receivers 2xtime of flight distance is based on all devices using the FM_CW input signals.

In order to complete the synchronization of multiple devices, we need to provide a common digital clock, and SYNC input to start the timing engine.

If you are trying to cause the FM_CW Chirp output to be timed to an external event (example external time reference), you would trigger the SYNC_IN on all devices. This matches the digital timing engine between slave devices. The SYNC_OUT from the master device, is sent to an external conditioning circuit, the time synchronization occurs in external logic, the buffered SYNC_IN signals are sent to ALL Radar sensors, so that there digital timing is aligned.

Additional information will have to be added to the Schematic and Layout guide for the CASCADE use case. www.ti.com/.../getliterature.tsp

Note: in addition you need to have the CLKP come from a buffered TCXO or disciplined clock source. a 1v PtP 40Mhz clock is sent to trace length matched clock traces. The clock input at the device is AC terminated with a series cap, and pulldown termination resistor. For the CLKM input a termination resistor to Ground is used.

3) the maximum number of slaves has not been evaluated, a Cascade of 2 devices, and a Cascade of 4 devices has been attempted. Related to (1) the 19.25Ghz (chirp / 4 in frequency) needs to not be degraded in Transmitter quality.

The SYNC_IN, and CLK_P buffering can be extended to more devices.
The power needed to drive the AWR1243 devices, is normally one PMIC for every two devices.
The FM_CW_CLKIN, FM_CW_SYNCIN power level for each device, has only been evaluated for a passive power splitter of 4 AWR1243 from one master.
If there is an active LNA, and power splitters, I think more devices could be cascaded, but there is no customer experience for this yet.

4) The Radar Sensor has 12bit A2D conversion, the DFE block after this is performed with 16bit precision. The output of the DFE is saturated and rounded to 12/14/16bits. The HSI (CSI-2 or LVDS format) is normally output in the resolution of the DFE.

5) Heat dissipation - there are several TI documents and references in the datasheet. Under the tools folder for the AWR1243, there is a power estimation spreadsheet. This provides an average power estimate. I looked on the AWR1243 tool folder, the model spreadsheet is not present today, you can use the one on the IWR1443 page, swww.ti.com/.../getliterature.tsp
select the IWR1443, you will need to estimate the use case, you will need
some use-case, ambient temperature, bandwidth, radar parameters
Chirp Parameters - www.ti.com/.../swra553.pdf

use the mmWave Sensing Estimator tool - www.ti.com/.../mmwave-sensing-estimator

Once you have the power / radar profile, you then need to decide the heat extraction method. If its through the device ball connections to the board (conduction), or forced air cooling over a heat sink (conduction and convection). The AWR1243 datasheet, Section 5.8 discusses the thermal transfer characteristics.

Note: it is good to design for a die temperature of 95C or less to increase the Power On Hours. Section 5.3 of the datasheet has the Power On Hours for automotive applications. The Embedded Processor POH estimation guide can be used, www.ti.com/.../sprabx4.pdf

There is some information, on layout - heat dissipation, in the schematic and layout design guide.
www.ti.com/.../getliterature.tsp

6) TSW1400 EVM is a High Performance Analog evaluation platform with HSDPro software, for LVDS data converters. While there maybe enough LVDS lanes to support, 2 data lanes, sync, and a clock (4 per AWR1243), we will have to find out about the number of allowed clocks. The firmware / FPGA code question is not known, we will have to get back to you.

7) EVM schematic and Layout was done in the Cadence tool flow.

Regards,
Joe Quintal