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AWR1243: Cascading AWR1243

Faiz Ahmed
Intellectual 460 points
Part Number: AWR1243

Hello,

1) I was wondering, what the acceptable loss, return loss, coupling and phase imbalance are if we split the 20 GHz LO signal?

2) From my understanding, the master low frequency sync out signal (SYNC_OUT) signal is fed into slave sync in signal (SYNC_IN). The SYNC_OUT signal is also used for the SOP signal for flashing.

2a) Do you see any issue if the master SYNC_OUT signal is used for SOP and then fed into a slave SYNC_IN signal?

2b) Does the SYNC_OUT signal have to be conditioned if it's driving more than one slave?

Thanks,

Faiz

  • 0
    TI__Mastermind 23725 points

    Hello,

    Posting the response from your our experts as below:

    SOP(n) are input pins.   They must be present when nRST is released.

    You need to check on the default pin muxing use.

    If you want to re-assign this to be a SYNC OUTPUT.   It should be done after boot.

    I thought the recommendation was to generate a software SYNC OUTPUT, buffer this with a 1/n device,

    And send that to all SYNC Inputs, so they are driven nearly at the same time.

    Thank you,

    Vaibhav

  • 0 in reply to Vaibhav Mahimkar
    Intellectual 460 points

    Hello,

    Thanks for the information. That makes sense.

    Another question we had was regarding the OSC_CLKOUT signal (pin A14). In the datasheet, it says it can be used by slave chip in multichip cascading. Would this act as the digitial  reference clock? How do we connect that between master and slave?

    Thanks,

    Faiz

  • 0 in reply to Faiz Ahmed
    TI__Guru 58035 points
    Hello Faiz,
    In the cascade mode the the OSC CLOCKOUT can be used to take the 40Mhz reference clock from the master and fed to the slave. On the slave side this is fed on the XTAL_P pin of the slave device, instead of the XTAL. This way both the master and slave both operate on the same 40Mhz reference clock.

    Regards,
    Vivek