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AWR1243: Development and Release of Bus Functional Model for AWR sensors

Part Number: AWR1243

Is there a plan to make available a VHDL or Verilog/SystemVerilog BFM for the AWR product family? The programmer's guide is helpful (SWRA555), but I find documentation can lag chip design by several months. Would be better for my developments to use what your verification engineers are using to limit surprises when we receive chips. Thanks.

  • Hi Jonathan,

    There is no plan to release the HDL equivalents of mmWave devices. The mmwave devices interact with external world via standard interfaces, and as such, compliance of external devices to these interfaces will imply compatibility with mmWave devices.
    Was there anything specific you were concerned about and we could guide you accordingly to alleviate such concerns.

    Thank you,
    Vaibhav
  • Yes, not the physical interface but the data definition. This is not for the control path but the data paths over LVDS or CSI2.
  • Hello Jonathan,
    Incase of CSI2 the interface and specs are well defined by the MIPI standard. Is there anything specific information you are looking for for these interfaces?

    Regards,
    Vivek
  • For now this is acceptable. I believe I made my point about project risk coupled with the fact the high speed interface has issues where TI has provided a work around. I think in the future it would be prudent for TI to consider making available a BFM available. This leads to an executable interface specification rather than a documentation driven one. Model Based System Design is getting more and more popular, BFMs make this possible. Thanks for the help.

  • Hello Jonathan,
    Yes, we do understand your point. we will look into it for the future.

    Regards,
    Vivek