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OPT9221: Drive TIC_CLK in master serial configuration mode with external hardware

minghua
Intellectual 495 points
Part Number: OPT9221
Other Parts Discussed in Thread: OPT8241

Hi, We are trying to boot up an OPT9221/OPT8241 combo from an EEPROM but without FX2. Got a few questions as to how to drive TIC_CLK because we are seeing no clock activity and deduced the clock needs to be driven from an external source. We also got some confusion.

From the opt9221.pdf document, the pin H1 is named "TIC_CLK" and marked as "input".

But on the reference schematic, there are two pins one named "EXT_TIC_DCLK_IN", and another "TIC_DCLK". Are they the same signal (maybe only tied together in master serial configuration mode)? Are they the same as "TIC_CLK" in opt9221.pdf? 

Just would like to clarify the signal mentioned is used to drive the clock on the OPT9221 EEPROM for master serial configuration mode.

In the opt9221.pdf, the figure 17 shows in master serial configuration mode the TIC_CLK is driven from a "Device". Is this device an OPT9221 chip? If so, now it changes from an "input" to an "output". Is this just a typo?

How should we drive this TIC_CLK? We already drive SYSCLK_IN with a 48MHz crystal. Can we drive TIC_CLK with the same clock source at the same frequency? We captured the OPT9221 chip is driving TIC_CSOZ low for about 600ns every few hundred milliseconds, now that it must be derived from the 48MHz SYSCLK_IN. If we drive TIC_CLK at a different speed than SYSCLK_IN, would that be a problem?

Or if this can be an output pin on OPT9221, OPT9221 would output a clock signal to drive the clock on EEPROM. Is that possible and how to make that work?

Update: Since Anand answered this pin is an output driven by OPT9221 in master configuration mode. Now that we are seeing TIC_CSOZ being driven low for about 600ns every few hundred ms. But when probing we see TIC_CONF_DONE keeps low from the beginning and in the whole time line, and INT_OUT rises with power then keeps high.

Since TIC_CSOZ is driven, can that mean the master serial configuration mode has been configured right? We have checked the boot[2:0] to be 011 that should be correct, but will double check again.

  • 0
    TI__Genius 15005 points
    Hi,

    Yes, TIC_DCLK and EXT_TIC_DCLK_IN in the schematics are the same as TIC_CLK in the datasheet

    If you are trying to boot the OPT9221 from an external source, you need to ensure that the BOOT[2:0] pins are appropriately configured as in Table 38.

    TIC_CLK should be driven by an external source when using slave serial or slave parallel boot modes.
    TIC_CLK will be driven by OPT9221 when using master serial boot mode.
    So TIC_CLK will be an input in slave boot modes and will be an output in master boot modes.
    This is not clear in the datasheet right now, and we will clarify it in the next version.

    Yes, the "Device" block in figure 17 to figure 19 in the datasheet refers to the OPT9221.

    There is no lower restriction on the TIC_CLK frequency, but we have a minimum clock period requirement of 15ns.

    Best Regards,
    Anand
  • 0 in reply to Anand Gadiyar
    Intellectual 495 points

    Hi, Anand,

    Thanks for the quick response. I updated the question with a drawing, and a few further questions with this update. We are still not able to get OPT9221 up and running.

    Since I see TIC_CSOZ is not mentioned in slave boot modes, I deduce that seeing pulses on it means the OPT9221 is running in master serial configuration mode. Is this correct? Can we also deduce the OPT9221 is running properly thus the input 48MHz SYSCLK_IN is ok?

    If the TIC_CLK is driven by OPT9221, what frequency should we see on it?

    We are not seeing the high part at the beginning of TIC_CONF_DONE, what could be the cause to it?


    What signals should go into the "Config Pins" of the figure 16? I can see there are more signals to probe to verify the timing in slave modes, but cannot see such detailed timing diagram for the master mode. Should we see activities on TIC_CONF_DONE, TIC_STATUSZ, TIC_INIT_DONE?

    Thanks!

  • 0 in reply to minghua
    Intellectual 495 points
    After some playing around, the CONF_DONE eventually finishes in 200ms to 250ms. But INT_OUT still does not show as expected, though hopefully it won't be a problem because we don't rely on it.