Hi,
In datasheet, it only explained that OSC_CLKOUT is Reference clock output from clocking sub system after cleanup PLL. But what's the frequency? Will it change based on chip configuration or it is a fixed frequency?
Thanks,
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Hi,
In datasheet, it only explained that OSC_CLKOUT is Reference clock output from clocking sub system after cleanup PLL. But what's the frequency? Will it change based on chip configuration or it is a fixed frequency?
Thanks,
Hello Chris,
We have asked one of the designers for the functions, bit definitions that match the TRM Figure 3-1 for the clock subsystem. From Vivek's description, the preliminary answer is the OSC_CLKOUT frequency matches the APLL output frequency, and the divider programmed.
In IWr14 device, the APLL frequency would be based on the highest speed peripheral which is HSI(LVDS/CSI-2).
Given an external crystal at 40Mhz, and an 1800Mhz output, the feedback divider would be 45. In this case the OSC_CLKOUT would be 1800Mhz.
I think it would be a better idea to divide this signal back down to < 150Mhz for single ended CMOS use.
In the datasheet IWr16, under the pinmux table, Table 4-1, K13, you can select the PMIC_CLKOUT, using addrexx 0xFFFFEA64 to select the PMIC_CLKOUT
I think the proper divider is 1800/2 = 900, for a 2Mhz output.
We will send more of an update, when the designer has provided more information.
Regards,
Joe Quintal