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AWR1243: Clarifications on modes and frames

Part Number: AWR1243


 We are trying to understand the different frame formats and different modes supported by AW1243 transceiver. We have referred to the following documents: AWR1xxx_CSI2.pdf, sqra555.pdf etc.

1. We would like to use Packet0-format1 for getting the ADC data. Please confirm that this format works for both Interleaver and Non-Interleaver modes.

2. In this format, between LineStart and LineEnd short packets, one chirp/line of ADC data, corresponding to each of  the enabled ADC channels is accomodated. Please confirm.

a. In case of Interleaver mode: LS -> Rx00 Rx10 Rx20 Rx30 Rx01 Rx11 Rx21 Rx31.......Rx3N -> LE

b. In case of Non-Interleaver Mode:  LS -> Rx00 Rx01 Rx02 Rx03.....Rx0N   Rx10 Rx11 Rx12 Rx13.......Rx3N -> LE

3. The interleaving depth is always 1 sample in Interleaver Mode. Please confirm.

4. If 16-bit ADC samples are being sent as RAW8, do we have to swap the 8-bit data or is it just pure concatenation?

5. We will be mostly using RAW12/14 formats with chirp sizes of 128/256/512/1024. With the "mipi unit" calculations, I am thinking no "Null Packets" will be inserted. Please confirm.

6. Is there a provision to get the Chirp Quality information on any other interface other than as part of MIPI packets? Eg, can application SW read any registers/buffers in the transceiver using SPI or some other low frequency interface for this data, periodically?

Appreciate your early response.


  • Hello Rajani,
    Please find my reply below:
    1) Yes we do support both interleaved and non interleaved formats for ADC data (packet 0- format1).
    2) Your understanding is correct, one chirp data from all the enabled channels would be sent out on the CSI interface in one long packet between the line start and line end.
    3) The interleaving depth is 1 sample in interleaved mode.
    4) We follow the MIPI CSI2 standard for the RAW8 format. The LSB is sent out first and then the MSB.
    5) Are you using 12/14 bit ADC data width ? In that case, yes there would be no null packets inserted.
    6) The CQ data comes out only on the high speed interface along with the ADC data. Since the CQ data is associated with every chirp it needs to be synchronized with the ADC data of that chirp and hence they are sent out over the same interface.

  • Thanks Vivek for the quick response, that was helpful.

    One more clarification needed-in one of your application document, the following is mentioned:


    2.1.2 Interleaved and Non-Interleaved Modes

    The data corresponding to all the configured receive (Rx) channels are stored in the ADC buffer. There

    are two possible storage formats of the data in the ADC buffer with each format best suited (also

    recommended) for use with a particular variant:

    On AWR12xx and XWR14xx device variants, the interleaved mode of storage is recommended as it

    also facilitates easy mapping and transfer of each Rx channel data over a corresponding lane.

    • On the AWR16xx device variants, only the non-interleaved mode of storage is supported, which makes

    it more conducive for the processing of the ADC data by the DSP processor.


    Here "lane" is CSI lane? Is there a dependency on number of ADC channels or mode of operation in deciding the number of CSI lanes? Please clarify.

  • Also, one more question.
    Is the Chip Quality data size always 680 bytes irrespective of chirp length? Even for a chirp length of 128bytes, will the CQ data be still 680bytes? Please clarify.
  • Hello Rajani,
    That is right, the lane here refers to the CSI lane. For example if you use 4RX and 4 CSI lanes in AWR1243 (which would be a common use case) , the non interleaved format allows you to send each of the RX channel ADC data on separate CSI lanes.

  • Hello Rajani,
    Thats right, in AWR1243 the CQ data size is fixed. It is 672 bytes.

  • :-( doesn't this mean that we actually have to hook up 4 CSIRx controllers?
    How about interleaved mode? If our configuration is 4Rx channels, and 4 CSI lanes, how is the data sent in interleaved mode? First a single stream of interleaved data is formed and then the "bytes" are sent in a round robin manner on the lanes. Is this correct? If so, what would be the reason for not following the same in non-interleaved mode? Appreciate your immediate response in this regard. We have actually finalized our board architecture with one CSIRx controller, which in this case may not work for non-interleaved mode.
  • BTW, is it non-interleaved or interleaved mode which has 1-1 mapping of Rx channel and lane? You are saying it is non-interleaved mode, but the document is referring to it as interleaved mode:

    On AWR12xx and XWR14xx device variants, the interleaved mode of storage is recommended as it also facilitates easy mapping and transfer of each Rx channel data over a corresponding lane.


    Please confirm.

  • Hello Rajani,
    I apologize, I meant interleaved mode can provide 1RX data on one CSI lane.

    Coming back to your concern, you need only one CSI receiver with 4 data lanes support. The difference between interleaved and non-interleaved mode is only the way the data need to be interpreted at the receiver end since the ordering of the data is different.

  • Hello Rajani,

    I would like to correct/clarify one of the points here:

    It is only on the LVDS lanes, there is a flexibility to map samples to lanes as there is no standard spec defining this. Hence, the statement "On AWR12xx and XWR14xx device variants, the interleaved mode of storage is recommended as it also facilitates easy mapping and transfer of each Rx channel data over a corresponding lane" corresponds to the LVDS transfers only. Thanks for bringing this up and we will update the document to specify this, in a future update.

    In case of CSI2, the MIPI spec clearly defines the mapping of the data on the lanes for the transfer. The CSI2 data transmitted from the AWR12xx/IWR14xx device will follow the spec.
    So your initial interpretation of interleaved/non-interleaved transfers (from the device) is correct. This data will appear as 8 bit information interleaved (interleaved here as per CSI2 spec) on each of the lanes.

    Hope this clarifies and addresses your concern.

    Best regards,
  • Thanks a lot Naveen for clarifying this immediately, we really got worried for a moment. We are good to go with this information.
    Thanks once again Vivek and Naveen for quickly resolving our queries.