DDC114: Offset values in Test mode

PETROS PETROU

Part Number: DDC114

Hi,

We are evaluating DDC114 and I am seeing some strange behaviour.

I am running the simplest config possible with a continuous 250Hz CONV (2ms Tint) , 4MHz CLK and trigger off DVALID to get 80bits of data while TEST is held high

I see that the first 2 values recieved (Inputs 4 and 3) are around 3000 counts (so slightly negative) while the next 2 (inputs 2 and 1) are around 4000 which seems more normal (around 0% full-scale). This 1000 negative offset is present when I leave Test mode and measure actual input currents.

My question is what is the expected value in a well designed PCB during Test mode and what can cause that offset on only 2 channels?

Thanks,

Petros

over 8 years ago

0 Praveen Aroul over 8 years ago

TI__Mastermind 49956 points

Hello Petros,

Can you let us know the output offset in non-test mode but with no input current applied on all the four channels?

0 PETROS PETROU over 8 years ago in reply to Praveen Aroul

Prodigy 75 points

Hi Praveen,

When I leave test mode in absolute dark conditions (my inputs are photodiodes) I get similar results so the first 2 values I read are 3100-3200 counts (inputs 4 and 3) and the next 2 are 4000-4100

Thanks

Sensors

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DDC114: Offset values in Test mode