IWR1642: question about TestPattern in test_adcbuf.c

Chris,

The TRM for the IWR devices provides information on the test pattern generation capabilities of the ADC Buffer. I have linked to this document below:

An explanation of the test pattern generator can be found on page 1118. Additionally, the register definition for TESTPATTERNVLDCFG which is used to configure the test pattern generator can be found on page 561.

Finally, Figures 12-1 and 12-2 provide a good visual explanation for how the test pattern generator works.

Please let us know if you need any additional information.

Regards,
Kyle

Kyle,

Thanks for your info! With your help, I found below code can configure the test pattern.

    /* Configure Test Pattern generation */
    testPatternConf.period = 255;
    testPatternConf.numSamples = sample;

    for (channel=0; channel < 4; channel++)
    {
        testPatternConf.rxConfig[channel].rxIOffset   = 0x0;
        testPatternConf.rxConfig[channel].rxIInc       =  0;
        testPatternConf.rxConfig[channel].rxQOffset  = 0xffff;
        testPatternConf.rxConfig[channel].rxQInc      =  0;
    }

But I still have question. What is the period for? As we uses continuous mode for test pattern, the test pattern will repeat continuously. This param seems no useful.

I also tried to capture the LVDS data by TSW1400 with High speed data converter Pro. But I found the first bit of the 16-bit data is inverted. That is, if I set pattern as above code, I got data with 0x8000, 0x7fff, 0x8000, 0x7fff. Why the first bit is inverted? My setting of High speed data converter Pro is as below. I changed the output data rate in HSDC Pro, but it seems no effect.

The continuous mode config I used is same as capture_demo_script_lvds_cont_mode.txt in sdk 1.0 capture demo for xWR1642 folder.

Hi Chris,

I am looking into this issue. I am running the capture demo with the test pattern you generated and am trying to trace the data all the way through to the HSDCPro capture to hopefully see where the bit is being flipped. Also, I am using the same configuration you did to ensure that our setups are exactly the same. 

Quick question, just to verify, when running the Capture Demo do you select :Option #3: MSS is responsible for Control Path and DSS is responsible for Data Path" or one of the other options?

Regards,
Kevin
 

Kevin Ortiz said:

Quick question, just to verify, when running the Capture Demo do you select :Option #3: MSS is responsible for Control Path and DSS is responsible for Data Path" or one of the other options?

I always tried with option 3.

Hi Chris,

We finally got some insight on why the MSB bit is being flipped. The .ini file in HSDCPro (in this case: AWR16xx_lvds_4Channel_ddr_4bit_par_centre_16_bit.ini) basically adds 0x8000 to every value received. This explains why the MSB bit is always flipped from what we expect. We are currently looking into what the purpose of this is and if it's possible to disable it.

Regards,
Kevin