Hello guys,
One of our customers observed an output data shift on DDC114.
Could you please help on the following questions?
-Questions
- When a CONV signal is shorter than minimum value or longer than maximum value, how behave the DDC114?
(If it’s undesirable for DDC114, customer wants to take measures.)
- Have you seen that an order of outputs data has been shifted in normal operation?
-Background
In the normal operation, the order of digital data output of both Side A and Side B are follows.
Input4->Input3->Input2->Input1
However, customer observed following order shift.
Input2->Input1->Input4->Input3
Once the output order is shifted, it keeps the order until power off/on.
Customer tried to reproduce this phenomenon, but they didn’t succeed. They observed it just once in debugging.
Customer will restart the reproduce test next week.
-Condition
A microcomputer controls CONV width adjustably from 333.3us(min). Basically, the DDC114 always operate for measurement.
While it is powered on, it sometimes software reset only the microcomputer asynchronously with the state of the DDC 114.
In that case, the control signal(MCU pin) to the DDC114 is initialized. As a result, CONV signal sometimes shorter or longer than the datasheet spec.
Customer concerns whether the CONV signal(longer or shorter than d/s spec) affects to the OUTPU order shift.
-Pin setting
OUTPUT format : 20bit (FORMAT = 1)
Mode : High speed (HISPD/LOPWR = 1)
Master clock : x1 (CLK_4X = 0), Appling 4.8MHz.
Your reply would be appreciated.
Best regards,
Kazuya Nakai.