Hi,
Would you pls help my below questions?
1. In 5.9.3.2 Typical Interface Protocol Diagram (Slave Mode) of AWR1243 datasheet, I found below info. Must it be two spi clocks delay or the min is 2 spi clocks?
Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI clock.
2. In Figure 5-5. SPI Communication, it seems that spi of AWR1243 will sample the data on the falling edge of the clock. Must it be falling edge?
Vivek,
I tried to detect the SPI signals on xWR1443 EVM+devpack when I click the spi connect button in radar studio. And I found the xWR1443 spi will detect the data on the rising edge of SPI clock as the signals shows below, instead of falling edge in the Figure 5-5. SPI Communication of AWR1243 datasheet. Would you pls help to check if it is a mistake in Figure 5-5. SPI Communication in AWR1243 datasheet?
ch1: spi_cs
ch2: spi_clk
ch3: spi_MOSI
