Hi Experts,
We have been facing a problem about the SPI communication between AWR1243 and an external FPGA.
After NRESET is set to HIGH, INTR becomes and keeps HIGH.
So, during this condition, SPI communication seems that it might not be working properly.
Could you please look into it and let us know your observation?
The attached file shows each line level when NRESET is set to HIGH.
If you need any other information, please let me know.
Best regards,
Hitoshi
7532.20170814_TI_AWR1243_NRESET.pdf