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AWR1642: Some question about the bootloader of AWR1642.

Xiao Du
Intellectual 410 points
Part Number: AWR1642

 Hello , 

the "DSS.bin" and "MSS.bin" are combined to be one file named "xxx1642xxx.bin", there are some  questions:

Q1:    the qspiflash driver test has code like"flashAddr = flashAddr + 0x180000U" , qspiflash test code write data to SFLASH start at  flashAddr + 0x180000U ( flashAddr = 0xC0000000 ) ,  is that means  "xxx1642xxx.bin"  was stored in 0xC0000000->0xC0180000 in FLASH ?

Q2 :   when the bootloader load "xxx1642xxx.bin" from FLASH to RAM,Where is the load start address of MSS code and DSS code in FLASH ? 

Q3:    If I dont want to write FLASH by  TI flah tool , I wanna write MSS image and DSS image to SFLAH via my own program , what should  I  pay attention to about the bootloader in ROM ?

  • 0
    TI__Mastermind 21025 points
    Q1: Yes.

    Q2: You will need to consult the .map files for each image. It will show you the entry point (_c_int00), and RAM locations for each function in the .text section.

    Q3: Please download the bootloader document (search SWRA563 on ti.com). It will contain the details you are looking for.
  • 0 in reply to db_woodall
    Intellectual 410 points

    Hello , db_woodall

    I have known the start address of entry point in RAM .Now, I want to know where is the start address in flash 0xC0000000 - 0xC0180000 when I get the image( MSS image, DSS image) .for example, MSS code's start address is 0xC0000040 and MSS code size is 0x4000.Is that means the BSS code's start address is 0xC0004040 ?

    .

  • 0 in reply to Xiao Du
    TI__Expert 5025 points

    Hello Anist,

    You may refer to the mmwave_sdk_<ver>\packages\scripts\ImageCreator\xwr16xx\Image_Creator_User_Guide.pdf to understand the multi-core image format that the bootloader works with.

    For the correct operation, the multi-core image must reside at memory mapped location 0xC0000000 (equivalent to address 0 of SFLASH). The ROM bootloader looks for an image at this offset. The multi-core image has binaries for MSS, Radar SS and DSS. These are loaded to the respective program memories (TCMA - MSS, Radar SS and L2 memory - DSS).

    The QSPI test application is randomly choosing an offset location for the test. This is only a reference application to showcase the SFLASH access (read-write). The actual offset may be chosen based on the size of the SFLASH used and the choice of offset. Please ensure that you atleast start from a sector beyond the size of the multi-core image (for ex. xwr16xx_mmw_demo.bin) to load any other image/data that the bootloader will not interpret.

    Best regards,

    Naveen