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OPT9221: OPT9221 master mode how to program the configuration registers

minghua
Intellectual 495 points
Part Number: OPT9221
Other Parts Discussed in Thread: OPT8241

Hi,

Following the conversation on the thread titled "OPT9221 Master Serial Configuretion", it mentions "an external reset to be done followed by register programming as required". Where we can find the sequence of the registers to be programmed? We have followed the CDK hardware design but without the FX2 microcontrollor. From the OPT9221 datasheet I see TG_DIS needs to be set to 0 to get system sequence started. Any other registers will have to be programmed to just start to see data frame coming out?

Based on reading of the thread for 4-lan serial mode, the other user configures only sysclk frequency at 0x33 of DE registers, then set TG register 0x80 to 0 to get the streaming started. That means with just the default settings, and then set TG 0x80 to 0, it is all needed to get the streaming data started. Is this correct?

However when I try to write to DE 0x33 with 0x010030 (which defaults to 0x000030), the register value does not change. Though we do have sysclk at 48MHz, I just try to modify the register to see whether I can write to it. This means the I2C write has a problem, does it? If it is a I2C write problem, what could be the cause?

Thanks.

  • 0
    TI__Mastermind 49926 points
    Hello Minghua,

    We have received your inquiry regarding the device OPT9221 and the applications team will get back to you with a response shortly.
  • 0 in reply to Praveen Aroul
    Intellectual 495 points

    Hi, Praveen, Great to get some response from you. How do you think about my problem?

    It's still a problem that we can read all the TG and DE registers, but if we write to them the I2C succeeds but when read back the value does not change.

    When reading TG 0x2 register, the datasheet states default value should be 0, but we get 0x18. Can this be some indication of a problem? All other TG registers at 0xc, 0xd, 0xe, 0xf, 0x12, 0x20, 0x21, 0x22, 0x80, 0x81, 0x82, 0x83, 0xcc, 0xd6 are getting default values back.

    The DE 0x1 register default is 0x1xx, but read 0x80031d. Does this say something? Tried othe DE registers at 0x0, 0x2, 0x3, they are getting correct default values.

    I also see another thread about connect the opt8241 to external HW. It mentions "TFC_HD _BD_OUT(This is the write enable) ... ". Should the BD/HD signal be tied high or low to enable write?

    Yet another thread about OPT9221 boot suggests to set sleep/ready/cez to 0/1/0. I'll examine that to confirm. If nothing works, probably I'll probe the CDK by disabling the FX2 as the above thread "connect the opt8241 to external HW" suggests. Any other ideas?

  • 0 in reply to minghua
    TI__Expert 3495 points
    Minghua,

    Can you tell us the "big picture" of what you're trying to accomplish? Are you using Voxel SDK to set these registers or direct I2C I/O using your own tools? Have you tried to compare your results with what Voxel Viewer is giving you?

    -Larry
  • 0 in reply to Larry Li
    Intellectual 495 points

    Hi, Larry, The bigger picture is that we replaced FX2 with our own external processor. It is no different than the other thread I quoted earlier.

    I'm programming OPT9221 directly through I2C.

    No I have not compared to the voxel viewer. Are all the registers configured by the viewer, not the FX2? If that is the case it is a good suggestion from you that I shall look at the viewer how it configure everything for certain features. But let me ask a simple question: if I don't do anything else, just write a 0 to TG register 0x80, should the framing data start to come out? By framing data I mean we start to see HD and VD toggling to form a frame.

    Thank you for helping us.

  • 0 in reply to minghua
    Intellectual 495 points
    Eventually we figured out just need to pull pins ready/overflow/sleep to 1/0/0. Then configure TG register 0x80 to 0. That's all needed to get the frame data coming out.