AWR1243BOOST: Basic Interface Questions

Richard Raffanti

Part Number: AWR1243BOOST
Other Parts Discussed in Thread: AWR1243

Hello, I've been contracted to build a data interface from the AWR1243BOOST development board to an FPGA board with the goal of continuously streaming data to a PC. I've read through a lot of the available tech documents, and have a couple very basic questions, which I wasn't able to resolve.

First, it wasn't clear to me if the same data is available via the LVDS interface as is available via the CSI2 interface. The data lanes on the chip are labelled "CSI2_TXP(M)" etc; are these also used for the LVDS outputs (and therefore, there are the same four lanes available for the LVDS IF as are available for the CSI2 IF)? I'd like to avoid implementing the CSI2 PHY circuitry if possible. Also, what is the function of the "HS_DEBUG" pairs? I don't see them referenced in any doc, so maybe I haven't found the correct doc.

Second, related to this, does swru520a Technical Reference Manual (or some portion of it) apply to the AWR1243? Its title implies it refers only to the AWR14XX and AWR16XX, though its listed under the AWR1243 family in your document navigator. (Don't want to wade through the 2832 pages if it doesn't apply!)

My plan is to use the AWR1243BOOST plugged into the MMWAVE-DEVPACK board, then make a board to adapt the either 60-pin QSH or the 120-pin connector on the DEVPACK to an FMC, which would plug into an FPGA devboard. Does that seem like a workable approach?

Thanks for your help.

Rick

over 8 years ago

0 Abdulraheem Killedar over 8 years ago

TI__Expert 3610 points

Hello Rick,

AWR1243 supports only the CSI2 interface as the interface for RAW ADC data transfer out of the device. Also swru520a is Tech Refence manual for AWR14xx/16xx and not for AWR1243. For AWR1243, Which is a RADAR front end with SPI interface to control the device and CSI2 interfae to take out the ADC output for post processing. You may refer to the datasheet for the same.

The LVDS interface on this device is not supported in production devices.

regards

0 Abdulraheem Killedar over 8 years ago in reply to Abdulraheem Killedar

TI__Expert 3610 points

Additionally, LVDS interface in case of AWR1243 is a debug interface and the ADC raw data can be taken out of the devie through LVDS interface for debug. This LVDS interface has 7 pair of differential signals with 4 -data lanes, 1- LVDS clock,1- LVDS FRCLK, 1-LVDS VALID signal.
The data and clock lanes are muxed with CSI2 lanes. The HS_DEBUG1/2 represents the LVDS FRCLK, LVDS_ VALID respectively .

regards
AK

0 Richard Raffanti over 8 years ago in reply to Abdulraheem Killedar

Prodigy 160 points

Hi Abdulraheem,

Thanks much for your prompt replies. Your second reply seems to contradict your first: to clarify, the LVDS interface *is* supported in production silicon of the AWR1243?

Best regards,

Rick

0 Richard Raffanti over 8 years ago in reply to Richard Raffanti

Prodigy 160 points

Hi Abdulraheem,

Still hoping for a clarification on this, as it seems that one answer says that the LVDS is not supported on production silicon of the AWR1243, and the other one says that it is.

Thanks,

Rick

0 Abdulraheem Killedar over 8 years ago in reply to Richard Raffanti

TI__Expert 3610 points

Hello Rick,

LVDS interface on AWR1243 is supported as debug interface(like in TSW1400 setup) but not as the data interface for the raw ADC data transfer to Host processor for post processing . Hope this clarifies.

Let us know if you need any further information

regards

0 Richard Raffanti over 8 years ago in reply to Abdulraheem Killedar

Prodigy 160 points

I think I understand. It sounds like the LVDS interface will work for our application, in which we'll be connecting those seven pairs to an FPGA for continuous streaming of data to a computer. Can you point me to some document that more fully describes the LVDS interface? I have read through swra555.pdf, and I see, for instance, in sec 5.1, the packet structure. But where is a timing diagram which describes the "FRAME_CLK" and "FRAME_VALID" signals you mentioned in an earlier response?

Thanks for your help.

Rick

0 Abdulraheem Killedar over 7 years ago in reply to Richard Raffanti

TI__Expert 3610 points

Hello Rick,

Please find the timing diagram as below. We are in process of updating the swra555.pdf with the same information

regards

0 Richard Raffanti over 7 years ago in reply to Abdulraheem Killedar

Prodigy 160 points

OK, so it looks like the FRCLK signal provides word alignment to allow forming 32-bit words from a series of 8 4-bit words. What does the FRAME_VALID signal do? (it's not shown in the timing diagram, though you mention it in an earlier response)

Rick

0 Richard Raffanti over 7 years ago in reply to Richard Raffanti

Prodigy 160 points

Never mind, I found the answer here:

e2e.ti.com/.../614946

Thanks fpr your help.

Rick

Sensors

Sensors forum

AWR1243BOOST: Basic Interface Questions