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CCS/PGA900EVM: Current loop limited to 3.8mA to 22mA

Part Number: PGA900EVM

Tool/software: Code Composer Studio

Hi, I have been doing some testing with the PGA900EVM. I recently picked it up again to do some tests of the current loop output. I was surprised to find that I can only get it to set the current between 3.8mA and 22.16mA. I recall having been able to set the current as high as 30mA. I can't figure out what I'm doing wrong.

In my code I have the following lines to setup the DAC

    DAC_Config(DAC_ENABLE, DAC_RATIOMETRIC_MODE_DISABLE, DACCAP_EN | B_4_20MA_EN | DAC_VOLTAGE_MODE_DIS);

    AMUX_CONFIG(TADC_single_ended | TEST_MUX_P_EN | TEST_MUX_T_EN | TEST_MUX_DAC_EN);

The jumpers are set as described for 4-20mA mode.

J9, J4, J5, J10 - Closed
J6, J8, J7, J16 - Open
J19 - Set between pins 2-3
J14 - Set between pins 1-2

It's like the DAC saturates at around 11000 counts. Here is a graph showing my data. Current is measured at J10. Is this normal behavior?

  • Hello,

    Your settings are right. Has the voltage that you're powering the device with changed at all? Below 7V VDD you will start to see the current output of the DAC getting crushed in 4-20mA mode. The reason is an internal 40ohm resistor separating the device ground from the current loop basically shifting the ground up and lowering the actual voltage to the device.

    As long as you stay above 7V VDD you should not see this problem.

    Regards,
  • Hi Scott.

    Thanks for the reply. I figured out what the problem was by measuring V Out (TP30) for the corresponding DAC values as the graph above.

    V out also saturated around 11000 at VDD (3.5V). I then tried moving Jumper J11 to J13 so I supply the chip with a higher voltage for VDD. This solved the problem and the current goes to 30mA at DAC count = 16000.

    Can anyone confirm that it is the case, that when using the gate control feature to stabilize VDD at 3.5V, the current can not be driven higher than 22mA? I can not find this documented in the datasheet.

  • That is correct. The output current will be limited at lower VDD voltages.

    Regards,