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AWR1243: some questions regarding AWR1243

Shai Berman
Mastermind 7405 points
Part Number: AWR1243
Other Parts Discussed in Thread: AWR1642, AWR1443

Dear team

Hope you may help my customer, please see the below inquiries.

 

1)      The datasheet tells the following regarding VIOIN:



The maximum / minimum values match the 3.3V only. So can I use 1.8V for VIOIN? What are the limits (min/max) in that case?

What is the purpose of VIOIN_18? VIOIN is used to power ALL CMOS I/Os. May you clarify this issue please?

2)      There are two RF supplies: VIN_13RF1 and VIN_13RF2, which may be powered by 1.3V or 1V in bypass mode. How does the AWR knows to bypass its internal LDO in case of 1V supply? Should I connect the capacitor to the VOUT_PA in case of bypass?

3)      Is there some advantage of supplying VIN_13RF1 and VIN_13RF2 from separate external LDOs? Do these supplies share the same/different LDOs? There is a table 5-3 saying that the 1.3V consumers drawing 2A. May you tell the distribution of this current between VIN_13RF1 and VIN_13RF2 (in case they can be supplied separately)?

4)      May you tell the current consumption from each 1.8V supply? Should I supply quiet 1.8V for analog consumers (like Synthesizer, APLL, VCOs and etc.) separately from digital 1.8V consumers (like VIOIN_18DIFF)?

5)      Can I omit using the QSPI flash in case I would upload the device’s firmware patch via the SPI on each power-up/reset? In case I can, should I connect the unused QSPI pins to pull-ups/pull-downs? By the way, it can be seen from table 3-1 that AWR1243 doesn’t have QSPI … is it true?

6)      Are you planning to remove LVDS mode? Why it is called LVDS/Debug at table 3-1?

7)      Table 3-1 says that AWR1243 doesn’t have GP ADC. However, there are 6 GPADC pins according to table 4-1. What is true?

8)      According to AWR1243 errata (SWRZ071–May 2017), there is some crosstalk between CSI interface and RF TX (ANA#07). Do you know whether TI is planning to fix this bug? In case they are, may it influence the pinout?

 

If you can answer the questions above, I will really appreciate it. 

Thanks in advance

BR

Shai 

  • 0
    TI__Guru 50240 points
    Hi Shai,

    There are many questions here that I do not yet have answers for. I will talk to the AWR Team and ask someone to provide a response.


    Cheers,
    Akash
  • 0
    TI__Guru 58035 points
    Hello Shai,
    Please find my reply below:

    1) VIOIN_18 is needed for providing a bias voltage for the 3.3V GPIOs. On the 1.8V IO supply support, I shall get back to you on that.

    2) The user needs to inform the AWR device if it needs to bypass the internal LDO or not by using an API, there is no automatic detection. rlRfSetLdoBypassConfig is the API to be used to indicate that. In either of the cases the decap on the VOUT_PA pin is required.

    3) The reason we supplied the 1.3V using two outputs of the LDO is because of the current limit of the LDO. You can use a single LDO with sufficient current limit to supply both the RF1 and RF2 supplies. You can still keep separate routing from the LDO to the device pins between RF1 and RF2. The current between RF1 and RF2 is roughly equally split.

    4) You dont need separate supply sources for different 1.8V supplies. But over all the 1.8V supply needs to be "clean". You can refer to the datasheet for the noise requirements.

    5) You can omit the serial flash if you are downloading the code over SPI after each bootup. The AWR1243 device does have QSPI lines, but once we have the production device with the complete ROM the requirement of the serial flash almost goes away.

    6) The LVDS interface is intended for only debug and not planned to be productised.

    7) In the AWR1443 and AWR1642 we have GP ADCs not on AWR1243 since its a front end only device. Incase of AWR1243 those pins are used for internal debug.

    8) CSI coupling issue is targeted to be resolved on the silicon/package , there will be no ball out changes for this. For you it would be transparent.

    Regards,
    Vivek
  • 0 in reply to Vivek Dham
    Mastermind 7405 points
    Vivek, Thank you for your excellent support .
  • 0 in reply to Vivek Dham
    Mastermind 7405 points
    Vivek, there is any new regrading first question?
    still waiting for your reply on that.

    Thank you very much
    Kind Regards,
    Shai Berman
  • 0 in reply to Shai Berman
    TI__Guru 58035 points
    Hello Shai,
    Yes, we do support 1.8V IO configuration.

    Regards,
    Vivek