This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

IWR1443: Level meter application - technical questions

Expert 6460 points
Part Number: IWR1443
Other Parts Discussed in Thread: AWR1243

Dear Team,

our customer is developing a level meter with IWR1443. We would like to find out:

  1. Has TI mmWave team ever used circulator on 77GHz and can they recommend a design or component?
  2. Can you share comparison between immersion silver and gold plating surface finish on 77GHz? Up to now we have measurements on 10GHz to 36GHz frequency range from various previous projects but would like to know what we can expect on 77GHz. Will of course do our tests but if you have numbers to compare, it would help.
  3. Can you explain how we can use MCU_CLK_OUT pin to drive some external logic that requires clock? We have found description but we haven't found explanation how to use this pin.
  4. Do you have example on how to connect and synchronize multiple chips to form bigger phase array system?
  5. Can you provide phase noise measurements diagram?
  6. Can you provide temperature dependency of output power and sensitivity?

Thanks for your support,
Bartosz

  • Hi Bartosz,

    I've asked for assistance from several of my team members on these questions and I've CC'd you on all of these emails. The only question I can answer is the first and unfortunately the answer is no. We have not tested a circulator on any TI antenna design.


    Cheers,
    Akash
  • Hello,

    1) the RF circulator is used to magnetically separate the Tx and Rx ports using a common antenna.  This is not how the FMCW transmit antenna, and separate receive antenna are connected to the FMCW radar integrated devices.  No, we do not have experience using a circulator for this.

    2) the plating on the Rogers 4835 Lo Pro RF laminate immersion silver is used on the EVM.  Immersion gold, or Immersion tin are used for additional oxidation resistance.  The Rogers website has dicussions, along with board fabrication houses like Streamline Circuits.   On the Rogers website there are local Field Application engineers to discuss the application of the RF laminate, 4835 (EVM), 4830 (77Ghz automotive optimized), 3003 (test instruments - best performance).Since RF energy travels on the layer surface the plating affects the RF performance, along with the Coplanar waveguide, stripline, and surface layer grounding.

    3) In the device datasheets, 4.3 pin Multiplexing, MCU_CLKOUT register EA60h is used to control pin N9 to output a specific signal.   You would also use the Technical Reference Manual  TRM   , in the discussion section for the APLL clock divider.  The APLL takes the 40Mhz crystal or external clock, and multiplies this to an internal clock rate.  Using the TRM chapter, you would determine the high rate clock.   Then to have a 40Mhz clock output, you would set the APLL divider for the desired clock rate.

    4) Larger Phased Array systems, need to share a common RF Synthesizer ~19.25Ghz reference, this is called Cascade.  The AWR1243, xWR1443 have special applications for this.   The concept of large phased arrays needs to have RF Tx controls with different combined Tx operation.  The signals used are:

       FM_CW_SYNCIn(CLOCKIn) - 19.25Ghz external synthesizer input

       FM_CW_SYNCOut(CLOCKout) - master radar device 19.25Ghz synthesizer output

       SYNC_IN - Timing Generator start of frame external trigger

       SYNC_OUT - master radar device start of frame trigger output

       CLKP - an ac coupled 1.8v clock is sent to each radar device

       CLKM - resistor to GND

    There are additional limitations for the number of simultaneous Tx outputs, and the power supply for the 1p3v_RF1, 1p3_RF2 for more than 2 Tx at a time.

    5) please contact Vaibhav, we need to check if an NDA is needed to share the measurement setup diagram.  Typically for phase noise measurements you have

    special software, OSC_CLKOUT - measures 40Mhz clock conditioner output

    special software, MCU_CLKOUT - measure APLL divided clock output

    in Satellite or Single Radar Sensor, you would use Continuous chirp mode, and an external Clock input, and have a measurement antenna, test equipment to measure the Tx output.   In Cascade use, there is both the FM_CW_SYNCOUT(CLOCKOUT) 19.25Ghz, and the Tx outputs, in Continuous chirp mode.

    Please contact Vaibhav if characterization data is needed, this may require an NDA.

    6) please contact Vaibhav, this requires a characterization test graph, it may require an NDA

    The radar device datasheet on the RF characteristics, lists the published RF tested values.

    Regards,

    Joe Quintal

  • Hi Joe, hi Akash,

    thanks for your support and prompt feedback!

    We will have more questions moving on with the design!

    Kind regards,
    Bartosz

  • Hi Joe,

    feedback from customer:

    1) It is clear to have separate TX and RX antennas and in the first version of the design we will have same with IWR chip. However there is one specific application where we have to pack very narrow angle antenna (around 1,5°) in to 1"-1/2 tube and it is very hard, or almost impossible to have 2 antennas like this in that area. Even if we use dielectric lens that are common with this application. Number of patches required for this application in antenna to have 1,5° x 1,5° beam width is quite large even with 3mm wavelength. This is why we are searching solution for this application with circulator or some metamaterial directional coupler.

    3) Sorry - I was probably unclear in my question. In the document on the schematics there is basically only divider from few selectable internal clocks to the MCU_CLK_OUT pin. In the table 3.3 there is specified frequency range 20 to 25MHz defauls, 15MHz to 40MHz configurable. From the register EXTCLKDIV (if i have properly understand that this register is setting MCU_CLK_OUT divider) it is possible to have lower frequency on the output. We would need lower frequency for some external logic. So is there something running inside the chip on this clock limiting frequency range? And can I get it running on around 1MHz frequency?

    Thanks for your help,
    Regards,
    Bartosz
  • Hi Joe,

    could you provide feedback to 3)?

    Thanks and regards,
    Bartosz
  • Hello,

    1) related to circulators, we have not used them.   If the circulator had enough Tx to Rx isolation, I think the minimum is 15db, it would need to be tested.   You would have to modify or redesign an EVM with 1mm connectors.

    3) in Table 3-3, section 3.2.4, and the example of the divider for the PMIC registers, you can divide down the APLL clock to get a power of 2 divider.   The PMIC does not require an external clock, you could use the PMIC clock for external clock.

    Regards,

    Joe Quintal