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AWR1243BOOST: Is the SWRA555 document dated May 2017 the Latest?

Christopher Hanks
Prodigy 105 points
Part Number: AWR1243BOOST

Hi,

I have been using SWRA555 as documentation for understanding the data I see coming across the LVDS interface.  The documentation is somewhat incomplete when defining how non-ADC data moves over LVDS.  For example; how are headers mapped over lanes?  Where's the CRC?  What if data doesn't align to 128bit boundaries, etc.

Is there a newer revision of this document now or planned for the future? 

  • 0
    TI__Expert 5025 points
    Hi Christopher,

    Yes, there is a revision of the document planned and your feedback will definitely help in making the contents more complete. In the interim, if you have any specific queries, please feel free to post them on this forum.

    To answer your queries:
    1. The headers are mapped to the lanes as defined by the format mapping register. This is similar to the manner in which ADC data are mapped onto the lanes as explained in the doc.
    2. The CRC (ethernet CRC32) gets appended to the end of the data on each of the lanes. Please note that the 32bit CRC appear on the lanes with the frame clock toggling 16H,16L wrt to the bit clock.
    3. The data samples on the LVDS lanes are expected to align to the number of lanes selected.

    Best regards,
    Naveen