While decimation does reduce the effective data rate (discards actual samples and replaces with zeros) by a factor equal to the decimation factor, M=16, FCLK and DCLK stay the same as before decimation. Would it be more frendly for engineers if the output clk rate can be reduced according to the decimation factor?
For example, in the sonar filed, the interested signal frequency are always below 400kHz, but the AFE5809 has a lowest samping rate of 20MSPS, which means DCLK frequency is 140MHz for a 14 bit ADC. Imaging a PCB board that has one hundred channels (which is very common for some imaging sonars), and there will be a hundred high frequency traces on the board, this may make a big challange for hardware engineers.
If the output clk rate can be reduced according to the decimation factor M, then life might be better. for a M of 20, the actual output data rate is 1MSPS. considering the demodulation stage outputs are 16bit I channel and Q channel, each sample will have 32bits, then the output bit clk frequency could be only 16MHz (DDR).
