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AFE5801: Verilog HDL or VHDL code for AFE5801

user5144457
Prodigy 20 points
Part Number: AFE5801

Hello, 

I am trying to write the vhdl code to get the output data from the afe5801 using FPGA.

I am having trouble understanding how clocks work and digital output form（MSB? or LSB first?）, any reference Verilog HDL or VHDL code will be helpfull,

Thank you,

Best regards,

Li

  • 0
    TI__Expert 4145 points

    Hi Li,

    I'll recommend taking a look at the TSW1400EVM's  Verilog code here as a guide (for an Altera FPGA).

    The ADC's serial data bits are output on both the rising and falling edge of DCLK (DDR) and a single FCLK period represents an entire data sample (12 bits).

    I believe the device outputs LSB first by default but looking through some older documentation (unsure if still accurate), writing 0x10 to register 0x4 is supposed to put the device in MSB-first mode while writing 0x00 in the same register should be LSB-first. Again, I am not sure if this information is still accurate as the feature was removed from the register map in the latest datasheet.

    Sincerely,

    Olu