CCS/IWR1642: Driver of DMM interface on IWR1642

Hi Tiger,

Ive referred your question to IWR team and someone should have an answer for you sometime this week.


Cheers,
Akash

Hi Akash，

So far, I have not received a response to the IWR 1642 DMM driver (preferably with DEMO). When can I have an answer?

In addition, I have another problem, that is, the IWR1642 LVDS interface application. Since the LVDS interface does not have "VSync Start" and "VSync End" packets, then the ADC raw data I received from the LVDS interface will be aligned with CHIRP. Is there a frame head flag in the LVDS frame structure, so that I can detect the frame head flag to achieve alignment between ADC data and CHIRP, otherwise, how do I realize this function? I hope to have a reply as soon as possible.

Thanks,
tiger-zhang

Hello Tiger,

I am so sorry about this delay, I have asked two of our experts to take a look at this and we should have an answer for you on Monday.


Cheers,
Akash

Hello Tiger,

I am still trying to get an answer on the DMM driver. I should have a response for you sometime on Thursday.

As for your other question, the LVDS interface for 1443, and 1642 has a Frame Clock, the 0->1 transition is the start of Frame.
The Clock is a DDR style clock starting on positive edge (although polarity can probably be negative).
The Data is bit serial, the 1642 has Inphase on lane0, and Quadature data on lane1.

So with 16bit data, and 4 Rx channels for 2 lanes, there would be 16x4bits per sample.
If you had 128 samples per chirp, 16x4x128.
If you had 64 chirps per frame, 16x4x128x64 -> 524288 bits on each of two lanes, 262144 LVDS clocks.

See section 4.1 of the Datapath Programmers Guide, swra555.



Cheers,
Akash