Other Parts Discussed in Thread: AFE5809
I interfaced the AFE5809 EVM board with KC705 FPGA board with the help of ADC-FMC Adapter board. But I have to deserialize the LVDS interface in FPGA. I tried to convert the differential end to single end output and I sampled the data by bit clock as well as frame clock. But the sampled data looks wrong. Could you tell me how to use ISERDES2 logic in FPGA?
