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For the TMP100, I need to know the timing for it to send out data relative to the clock edge, I.e. time from I2C clock driven low (usually from processor) to data being valid on SDA line.
I refer to the figure below, which can be found on page 12 of the data sheet, which doesn't seem to make this information very clear.
Hello Ren
From my understanding of what you explained, this sounds like timing for Slave Receive mode.
What we want is timing in SLave Transmit mode.
How long is it from SCL going low to the data being valid ?
Thanks
Bob