Hi
As AWR1243 has the cascading ability to use multipal chips working simultaneously and each one of them has a CSI2 port. Though you recommend TDA3x for post processing (since TDA3x has 2 DSP core and 2 arm core so its processing capacity is good enough for our business), however each TDA3x only has one CSI2 port. . The point is when we use TDA3x for deployment, if there are N chips of AWR1243 cascading there need to be N chips of TDA3x for CSI2 port limitation, though for processing aspect one TDA3x is enough at all.
So in cascading situation we still prefer FPGA+DSP architecture， in one of your demonstration video you show a 4 chip cascading scenario, so I wonder what data gathering method do you use or recommend to use for this scenario.
By the way for now awr1243 is still in engineering samples phase,approximately when you could supply the release version？
Thanks!
Tom
