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AWR1243: AWR1243

Part Number: AWR1243

Hello

If a cascaded system with AWR1243 is considered, please help me with answer of some questions in both mode: single chip mode and cascaded chips mode.

The chips programming are done with SPI pins.

1- In datasheet, there are three pins called: SYNC_OUT, PMIC_CLKOUT and TDO that are connected to host processor with 47.5K resistors.In boost, these pins are used for SOP.

Can i ignore these connection?

2- can i ignore concection of PMIC_CLKOUT to host processor? if this connection shoud be to made, how to cannect this pin in Slave?

3- In page 4 of datasheet, it is said that AWR1243 chip does not have ability of JTAG but these pins are used in AWR1243boost !?

can i ignore these pins in connections? what will be the TDO pin? how shoud they be in SLAVE?

4- If SYNC_OUT of master to be connected to SYNC_IN of Slaves as well as Master, can i ignore connection SYNC_OUT of master to host processor for SOP? can i ignore 47.5K resistor?

5 In page 4 of datasheet, it is said that AWR1243 chip does not have ability of QSPI but these pins are used in:(datasheet,boost and even in the cascade document)!
can i ignore these connection when used SPI for programing, and in that case, can i not connect RS232TX and RS232RX pins (UART)?

6- We want to change the voltage level of IO's pins from 3.3 v to 1.8 v that will do this by changing the one of the output of the PMIC from 3.3 v to 1.8 v.

Is it just enough to data and clock pins of PMIC(AR_SDA , AR_SCL) are connect to Host processor and do not connect to RES pins of AWR1243?

can i ignore connections on RES pin in AWR1243?

thanks for your attention 

  • Hi,

    Can you please share more details about the overall cascade architecture?

    What is the host processor? How many chips will be cascaded? How do you plan to manage the clocks?

    Thank you
    Cesar
  • Hi
    thank for your attention
    I want to use ّFPGA as host processor. Also use 4 AWR1243 chips for the cascaded system.
    for digital fram synchronization: SYNC_OUT of master connect to SYNC_IN of slave as well as master. An 40MHz crystal connect to CLKP and CLKM of master and OSC_CLKOUT of master connect to CLKP of slave
  • Hello Tom,
    Please find below our reply to your queries:

    1- In datasheet, there are three pins called: SYNC_OUT, PMIC_CLKOUT and TDO that are connected to host processor with 47.5K resistors.In boost, these pins are used for SOP.

    Can i ignore these connection?
    [TI] The SYNC_OUT, PMIC_CLKOUT and TDO pins have dual functionality. During the device bootup the state of these pins is sensed and based on that the device boots up in different modes. After the bootup the same pins act as functional pins like TDO etc. These mode include flashing mode incase you want to use the QSPI flash, functional mode etc. The reason for taking these pins via the high impedance resister to the host is only to have an option for the host to control/change the SOP mode. If that is not desired you could just have pull up/down (>10K) to 3.3V option on the board itself to set the states of the SOP lines.

    2- can i ignore concection of PMIC_CLKOUT to host processor? if this connection shoud be to made, how to cannect this pin in Slave?
    [TI] I assume you are referring to the SOP pin functionality of the PMIC_CLKOUT pin here. In that case the above statement in point 1 is valid for both master and slave.

    3- In page 4 of datasheet, it is said that AWR1243 chip does not have ability of JTAG but these pins are used in AWR1243boost !?

    can i ignore these pins in connections? what will be the TDO pin? how shoud they be in SLAVE?
    [TI] JTAG interface need not be used for AWR1243. But the SOP functionality of this pin needs to be taken care of by using a pull resister.

    4- If SYNC_OUT of master to be connected to SYNC_IN of Slaves as well as Master, can i ignore connection SYNC_OUT of master to host processor for SOP? can i ignore 47.5K resistor?
    [TI] Again you need to take the SOP functionality into account. If not to the host processor, you need to have a pull on the board to have this pin the desired state during bootup.

    5 In page 4 of datasheet, it is said that AWR1243 chip does not have ability of QSPI but these pins are used in:(datasheet,boost and even in the cascade document)!
    can i ignore these connection when used SPI for programing, and in that case, can i not connect RS232TX and RS232RX pins (UART)?
    [TI] The QSPI flash can be used to automatically load the FW after bootup from the flash. The FW could also be loaded from the host over SPI interface every time on bootup. The only tradeoff between the two approaches is the time to load, the QSPI is much faster than the SPI interface.

    6- We want to change the voltage level of IO's pins from 3.3 v to 1.8 v that will do this by changing the one of the output of the PMIC from 3.3 v to 1.8 v.
    [TI] If you change the IO supply to 1.8V you need to take care that all the other devices interfacing to AWR1243 also operate at 1.8V IO level.

    Is it just enough to data and clock pins of PMIC(AR_SDA , AR_SCL) are connect to Host processor and do not connect to RES pins of AWR1243?

    can i ignore connections on RES pin in AWR1243?
    [TI] Yes, RES pins need not be connected.

    Regards,
    Vivek
  • Hello Vivek
    Thank you so much for your complete answers