Hi Expert,
We have a question related to TMP112 I2C communication for Acknowledge bit.
Please refer to below capture for I2C communication. Our observation shows that TMP112 will drive SDA low for acknowledgement at the falling edge of 8th SCL clock. At the 8th SCL clock, as we have not released SDA from master side, which cause mid-scale voltage.
Is TMP112 designed for give acknowledge at the falling edge of 8th SCL clock?
Thanks
Zhou