Hi,
I'm working on interfacing AWR1243 data output with another receiver chip using MIPI CSI2. I use five differential signals: four data lanes + clock lane. I need to put all five lanes to CSI2 low power state (LPS), i.e. put all ten physical signals to high level. When AWR1243 is idle (no chirps/frames are generated) four data lanes do move to LPS. However, a clock lane does not move to LPS. In fact, it continues to oscillate just like in HS state.
My question: how can I move clock lane to LPS (high level signal)?
Thanks.
